FPGA Central

OS: windows XP PRO
ISE version: 10.1.103

project properties:
cat: All
Family: Virtex2P
Device: XC2VP30
Package: FF896
Speed: -7

Top-level source type : HDL
synt tool: : XST
simulator : ISE Simulator
Prefferd language: : VHDL

Enable enhance design summary : <check>
Enable Message Filtering: < >
display incremental messges: <check>


synth, implement, and genearate all work successfully.

I switch 'sources for' from implementation to 'behavioral
simulation'

I right click on xc2vp30-7ff896
pick 'new source'

select 'vhdl test bench'
enter a filename 'abcd'
add to project <check>
click next,

new screen,
select a source with which to associate the new source,
the main process is already in blue,
click next,

new screen,
Project Navigator will create a new skeleton source with the following
spec:
Add to Project: Yes
Source Directory: C:\jon
\fpga_uarted_01\2009_01_26\LOKI_New_H_Project_VHDL \Code_Versions\10 -
New_Xilinx_Wrap_Data\LOKI_Top
Source Type: VHDL Test Bench
Source Name: abcd.vhd

Association: LOKI_TOP

I click finish, new screens all disappear, and the only thing under
xc2vp30-7ff896 is the same as before.

no abcd.vhd added, and I searched the whole C: drive no abcd.vhd.

what am I doing wrong?

jleslie48 wrote:
> OS: windows XP PRO
> ISE version: 10.1.103
>
> project properties:
> cat: All
> Family: Virtex2P
> Device: XC2VP30
> Package: FF896
> Speed: -7
>
> Top-level source type : HDL
> synt tool: : XST
> simulator : ISE Simulator
> Prefferd language: : VHDL
>
> Enable enhance design summary : <check>
> Enable Message Filtering: < >
> display incremental messges: <check>
>
>
> synth, implement, and genearate all work successfully.
>
> I switch 'sources for' from implementation to 'behavioral
> simulation'
>
> I right click on xc2vp30-7ff896
> pick 'new source'
>
> select 'vhdl test bench'
> enter a filename 'abcd'
> add to project <check>
> click next,
>
> new screen,
> select a source with which to associate the new source,
> the main process is already in blue,
> click next,
>
> new screen,
> Project Navigator will create a new skeleton source with the following
> spec:
> Add to Project: Yes
> Source Directory: C:\jon
> \fpga_uarted_01\2009_01_26\LOKI_New_H_Project_VHDL \Code_Versions\10 -
> New_Xilinx_Wrap_Data\LOKI_Top
> Source Type: VHDL Test Bench
> Source Name: abcd.vhd
>
> Association: LOKI_TOP
>
> I click finish, new screens all disappear, and the only thing under
> xc2vp30-7ff896 is the same as before.
>
> no abcd.vhd added, and I searched the whole C: drive no abcd.vhd.
>
> what am I doing wrong?
>

Try removing spaces from any paths (i.e. move your project from 10 -
New_Xilinx_Wrap_Data to 10_New...)

regards
Alan

P.S. I'm just guessing - generally spaces in paths and ISE don't mix...

--
Alan Fitch
apfitch at ieee
dot org

On Wed, 28 Jan 2009 13:26:20 -0800 (PST), jleslie48
<[email protected]> wrote:
>I switch 'sources for' from implementation to 'behavioral
>simulation'
....
>Project Navigator will create a new skeleton source with the following
>spec:
>Add to Project: Yes
>Source Directory: C:\jon
>\fpga_uarted_01\2009_01_26\LOKI_New_H_Project_VHD L\Code_Versions\10 -
>New_Xilinx_Wrap_Data\LOKI_Top
>Source Type: VHDL Test Bench
>Source Name: abcd.vhd
>
>Association: LOKI_TOP

all that looks OK and you FOUND the simulator page (took me a while!).
Which sim do you have? ISE sim or Modelsim?

.... but the question is, when
>I click finish,
what happens in the console window at the bottom? I see the
UnitUnderTest being compiled so that the wizard knows how to wire it up
for testing. Is that compilation failing? Might explain the problem.

Or, if the wizard won't play, just "add copy of source" a testbench from
one of the example projects into your project and edit it to suit.

- Brian
(LOKI? He's our cat!)

On Jan 28, 8:07 pm, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Wed, 28 Jan 2009 13:26:20 -0800 (PST), jleslie48
>
> <j...@jonathanleslie.com> wrote:
> >I switch 'sources for' from implementation to 'behavioral
> >simulation'
> ...
> >Project Navigator will create a new skeleton source with the following
> >spec:
> >Add to Project: Yes
> >Source Directory: C:\jon
> >\fpga_uarted_01\2009_01_26\LOKI_New_H_Project_VHD L\Code_Versions\10 -
> >New_Xilinx_Wrap_Data\LOKI_Top
> >Source Type: VHDL Test Bench
> >Source Name: abcd.vhd
>
> >Association: LOKI_TOP
>
> all that looks OK and you FOUND the simulator page (took me a while!).
> Which sim do you have? ISE sim or Modelsim?
>
> ... but the question is, when>I click finish,
>
> what happens in the console window at the bottom? I see the
> UnitUnderTest being compiled so that the wizard knows how to wire it up
> for testing. Is that compilation failing? Might explain the problem.
>
> Or, if the wizard won't play, just "add copy of source" a testbench from
> one of the example projects into your project and edit it to suit.
>
> - Brian
> (LOKI? He's our cat!)

sim is ISE but the original behavorial simulation was done using
Modelsim,
and I think its confused.

not a thing is showing up in the console window at the bottom quiet as
a mouse.
that is consistent with the fact that abcd.vhd was never created
either.

Loki - god of mischef.

On Jan 29, 8:00*am, jleslie48 <j...@jonathanleslie.com> wrote:
> On Jan 28, 8:07 pm, Brian Drummond <brian_drumm...@btconnect.com>
> wrote:
>
>
>
> > On Wed, 28 Jan 2009 13:26:20 -0800 (PST), jleslie48
>
> > <j...@jonathanleslie.com> wrote:
> > >I switch 'sources for' from *implementation to 'behavioral
> > >simulation'
> > ...
> > >Project Navigator will create a new skeleton source with the following
> > >spec:
> > >Add to Project: Yes
> > >Source Directory: C:\jon
> > >\fpga_uarted_01\2009_01_26\LOKI_New_H_Project_VHD L\Code_Versions\10 -
> > >New_Xilinx_Wrap_Data\LOKI_Top
> > >Source Type: VHDL Test Bench
> > >Source Name: abcd.vhd
>
> > >Association: LOKI_TOP
>
> > all that looks OK and you FOUND the simulator page (took me a while!).
> > Which sim do you have? ISE sim or Modelsim?
>
> > ... but the question is, when>I click finish,
>
> > what happens in the console window at the bottom? I see the
> > UnitUnderTest being compiled so that the wizard knows how to wire it up
> > for testing. Is that compilation failing? Might explain the problem.
>
> > Or, if the wizard won't play, just "add copy of source" a testbench from
> > one of the example projects into your project and edit it to suit.
>
> > - Brian
> > (LOKI? He's our cat!)
>
> sim is ISE but the original behavorial simulation was done using
> Modelsim,
> and I think its confused.
>
> not a thing is showing up in the console window at the bottom quiet as
> a mouse.
> that is consistent with the fact that abcd.vhd was never created
> either.
>
> Loki - god of mischef.

Did you look for the file in your project directory? Which
view did the source not appear in? Normally testbenches only
appear in the view for "Behavioral Simulation", not the
"Synthesis" view (default).

On Jan 29, 3:18 pm, Gabor <ga...@alacron.com> wrote:
> On Jan 29, 8:00 am, jleslie48 <j...@jonathanleslie.com> wrote:
>
>
>
> > On Jan 28, 8:07 pm, Brian Drummond <brian_drumm...@btconnect.com>
> > wrote:
>
> > > On Wed, 28 Jan 2009 13:26:20 -0800 (PST), jleslie48
>
> > > <j...@jonathanleslie.com> wrote:
> > > >I switch 'sources for' from implementation to 'behavioral
> > > >simulation'
> > > ...
> > > >Project Navigator will create a new skeleton source with the following
> > > >spec:
> > > >Add to Project: Yes
> > > >Source Directory: C:\jon
> > > >\fpga_uarted_01\2009_01_26\LOKI_New_H_Project_VHD L\Code_Versions\10 -
> > > >New_Xilinx_Wrap_Data\LOKI_Top
> > > >Source Type: VHDL Test Bench
> > > >Source Name: abcd.vhd
>
> > > >Association: LOKI_TOP
>
> > > all that looks OK and you FOUND the simulator page (took me a while!).
> > > Which sim do you have? ISE sim or Modelsim?
>
> > > ... but the question is, when>I click finish,
>
> > > what happens in the console window at the bottom? I see the
> > > UnitUnderTest being compiled so that the wizard knows how to wire it up
> > > for testing. Is that compilation failing? Might explain the problem.
>
> > > Or, if the wizard won't play, just "add copy of source" a testbench from
> > > one of the example projects into your project and edit it to suit.
>
> > > - Brian
> > > (LOKI? He's our cat!)
>
> > sim is ISE but the original behavorial simulation was done using
> > Modelsim,
> > and I think its confused.
>
> > not a thing is showing up in the console window at the bottom quiet as
> > a mouse.
> > that is consistent with the fact that abcd.vhd was never created
> > either.
>
> > Loki - god of mischef.
>
> Did you look for the file in your project directory? Which
> view did the source not appear in? Normally testbenches only
> appear in the view for "Behavioral Simulation", not the
> "Synthesis" view (default).

yeah I tried that, even did a search of the entire C:\ drive
it didn't make it.


I have solved the problem though. It's a bug in ISE 10.1.103
It simply will not let you re-run new source-->vhdl test bench
once you have done it once under modelsim and then switch the
properties to ISE simulator. I don't know if the problem has other
variations.

To get around the problem I made a brand new project from scratch
stating from the get go ISE Simulator. Added all the sources, SIG'ed
it (Syntesize, Implement, Generate) then switched to Behavioral
Simulation view,
added new source-->vhdl test bench ... and then it worked, actually
made the
testbench program:
-----------------------------------------------
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:27:37 01/29/2009
-- Design Name:
-- Module Name: C:/jon/fpga_uarted_01/2009_01_28_jl_mod/11jlmod/
ccuart01/source/loki_top_tb.vhd
-- Project Name: ccuart01
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: LOKI_TOP
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types
std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx
recommends
-- that these types always be used for the top-level I/O of a design
in order
-- to guarantee that the testbench will bind correctly to the post-
implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY loki_top_tb IS
END loki_top_tb;

ARCHITECTURE behavior OF loki_top_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT LOKI_TOP
PORT(
SYSTEM_CLOCK : IN std_logic;
RS232_DSR_OUT : OUT std_logic;
RS232_TX_DATA : OUT std_logic;
RS232_CTS_OUT : OUT std_logic;
RS232_RX_DATA : IN std_logic;
LED_0 : OUT std_logic;
LED_1 : OUT std_logic;
LED_2 : OUT std_logic;
LED_3 : OUT std_logic
);
END COMPONENT;


--Inputs
signal SYSTEM_CLOCK : std_logic := '0';
signal RS232_RX_DATA : std_logic := '0';


--Outputs
signal RS232_DSR_OUT : std_logic;
signal RS232_TX_DATA : std_logic;
signal RS232_CTS_OUT : std_logic;
signal LED_0 : std_logic;
signal LED_1 : std_logic;
signal LED_2 : std_logic;
signal LED_3 : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: LOKI_TOP PORT MAP (
SYSTEM_CLOCK => SYSTEM_CLOCK,
RS232_DSR_OUT => RS232_DSR_OUT,
RS232_TX_DATA => RS232_TX_DATA,
RS232_CTS_OUT => RS232_CTS_OUT,
RS232_RX_DATA => RS232_RX_DATA,
LED_0 => LED_0,
LED_1 => LED_1,
LED_2 => LED_2,
LED_3 => LED_3
);

-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

-- constant system_clock_period := 10ns;
--ERROR:HDLCompiler:806 - "source/loki_top_tb.vhd" Line 87. Syntax
error near constant
--ERROR:HDLCompiler:841 - "source/loki_top_tb.vhd" Line 87. Type error
near ns ; expected type void
--ERROR:HDLCompiler:69 - "source/loki_top_tb.vhd" Line 92.
system_clock_period is not declared

system_clock_process rocess
begin
system_clock <= '0';
--wait for system_clock_period/2;
wait for 10ns/2;
system_clock <= '1';
--wait for system_clock_period/2;
wait for 10ns/2;
end process;


-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100ms.
wait for 100ns;

--wait for system_clock_period*10;
wait for 10ns*10;

-- insert stimulus here

wait;
end process;

END;


-----------------------------------------------


although I kept getting an error on this line:

constant system_clock_period := 10ns;
--ERROR:HDLCompiler:806 - "source/loki_top_tb.vhd" Line 87. Syntax
error near constant
--ERROR:HDLCompiler:841 - "source/loki_top_tb.vhd" Line 87. Type error
near ns ; expected type void
--ERROR:HDLCompiler:69 - "source/loki_top_tb.vhd" Line 92.
system_clock_period is not declared

anybody know whats wrong with the syntax???

jleslie48 wrote:

> although I kept getting an error on this line:
>
> constant system_clock_period := 10ns;
> --ERROR:HDLCompiler:806 - "source/loki_top_tb.vhd" Line 87. Syntax
> error near constant
> --ERROR:HDLCompiler:841 - "source/loki_top_tb.vhd" Line 87. Type error
> near ns ; expected type void
> --ERROR:HDLCompiler:69 - "source/loki_top_tb.vhd" Line 92.
> system_clock_period is not declared
>
> anybody know whats wrong with the syntax???
>

You need

constant system_clock_period : TIME := 10 ns;

VHDL is a strongly typed language :-)

regards
Alan

P.S. Strictly there should be a space between the time value and the
unit as well, but some simulators will treat that as a warning.

--
Alan Fitch
apfitch at ieee
dot org

On Thu, 29 Jan 2009 05:00:51 -0800 (PST), jleslie48
<[email protected]> wrote:

>On Jan 28, 8:07 pm, Brian Drummond <brian_drumm...@btconnect.com>

>> (LOKI? He's our cat!)
>Loki - god of mischef.

Yup - that's our cat...
-Brian

On Jan 29, 4:17*pm, Alan Fitch <apfi...@invalid.invalid> wrote:
> jleslie48 wrote:
> > although I kept getting an error on this line:
>
> > *constant system_clock_period := 10ns;
> > --ERROR:HDLCompiler:806 - "source/loki_top_tb.vhd" Line 87. Syntax
> > error near constant
> > --ERROR:HDLCompiler:841 - "source/loki_top_tb.vhd" Line 87. Type error
> > near ns ; expected type *void
> > --ERROR:HDLCompiler:69 - "source/loki_top_tb.vhd" Line 92.
> > system_clock_period is not declared
>
> > anybody know whats wrong with the syntax???
>
> You need
>
> * constant system_clock_period : TIME := 10 ns;
>
> VHDL is a strongly typed language :-)
>
> regards
> Alan
>
> P.S. Strictly there should be a space between *the time value and the
> unit as well, but some simulators will treat that as a warning.
>
> --
> Alan Fitch
> apfitch at ieee
> dot org

you da man... will try that out first thing in the AM.

On Jan 29, 8:05 pm, jleslie48 <j...@jonathanleslie.com> wrote:
> On Jan 29, 4:17 pm, Alan Fitch <apfi...@invalid.invalid> wrote:
>
>
>
> > jleslie48 wrote:
> > > although I kept getting an error on this line:
>
> > > constant system_clock_period := 10ns;
> > > --ERROR:HDLCompiler:806 - "source/loki_top_tb.vhd" Line 87. Syntax
> > > error near constant
> > > --ERROR:HDLCompiler:841 - "source/loki_top_tb.vhd" Line 87. Type error
> > > near ns ; expected type void
> > > --ERROR:HDLCompiler:69 - "source/loki_top_tb.vhd" Line 92.
> > > system_clock_period is not declared
>
> > > anybody know whats wrong with the syntax???
>
> > You need
>
> > constant system_clock_period : TIME := 10 ns;
>
> > VHDL is a strongly typed language :-)
>
> > regards
> > Alan
>
> > P.S. Strictly there should be a space between the time value and the
> > unit as well, but some simulators will treat that as a warning.
>
> > --
> > Alan Fitch
> > apfitch at ieee
> > dot org
>
> you da man... will try that out first thing in the AM.

dumb-ass syntax checker. the CONSTANT declaration must be after
ARCHITECTURE

but before the BEGIN

Doh.

jleslie48 wrote:
> On Jan 29, 8:05 pm, jleslie48 <j...@jonathanleslie.com> wrote:
>> On Jan 29, 4:17 pm, Alan Fitch <apfi...@invalid.invalid> wrote:
>>
>>
>>
>>> jleslie48 wrote:
>>>> although I kept getting an error on this line:
>>>> constant system_clock_period := 10ns;
>>>> --ERROR:HDLCompiler:806 - "source/loki_top_tb.vhd" Line 87. Syntax
>>>> error near constant
>>>> --ERROR:HDLCompiler:841 - "source/loki_top_tb.vhd" Line 87. Type error
>>>> near ns ; expected type void
>>>> --ERROR:HDLCompiler:69 - "source/loki_top_tb.vhd" Line 92.
>>>> system_clock_period is not declared
>>>> anybody know whats wrong with the syntax???
>>> You need
>>> constant system_clock_period : TIME := 10 ns;
>>> VHDL is a strongly typed language :-)
>>> regards
>>> Alan
>>> P.S. Strictly there should be a space between the time value and the
>>> unit as well, but some simulators will treat that as a warning.
>>> --
>>> Alan Fitch
>>> apfitch at ieee
>>> dot org
>> you da man... will try that out first thing in the AM.
>
> dumb-ass syntax checker. the CONSTANT declaration must be after
> ARCHITECTURE
>
> but before the BEGIN
>
> Doh.
>
>

What us VHDL people call "the declarative region". All declarations must
be in a declarative region. You can declare a constant in a process,
procedure, function or architecture but it's got to be in front of the
appropriate "begin".

regards
Alan

P.S. I know there are other places declarations are allowed but "that's
not important right now"

--
Alan Fitch
Doulos
http://www.doulos.com

On Jan 30, 11:45 am, Alan Fitch <alan.fi...@spamtrap.com> wrote:
> jleslie48 wrote:
> > On Jan 29, 8:05 pm, jleslie48 <j...@jonathanleslie.com> wrote:
> >> On Jan 29, 4:17 pm, Alan Fitch <apfi...@invalid.invalid> wrote:
>
> >>> jleslie48 wrote:
> >>>> although I kept getting an error on this line:
> >>>> constant system_clock_period := 10ns;
> >>>> --ERROR:HDLCompiler:806 - "source/loki_top_tb.vhd" Line 87. Syntax
> >>>> error near constant
> >>>> --ERROR:HDLCompiler:841 - "source/loki_top_tb.vhd" Line 87. Type error
> >>>> near ns ; expected type void
> >>>> --ERROR:HDLCompiler:69 - "source/loki_top_tb.vhd" Line 92.
> >>>> system_clock_period is not declared
> >>>> anybody know whats wrong with the syntax???
> >>> You need
> >>> constant system_clock_period : TIME := 10 ns;
> >>> VHDL is a strongly typed language :-)
> >>> regards
> >>> Alan
> >>> P.S. Strictly there should be a space between the time value and the
> >>> unit as well, but some simulators will treat that as a warning.
> >>> --
> >>> Alan Fitch
> >>> apfitch at ieee
> >>> dot org
> >> you da man... will try that out first thing in the AM.
>
> > dumb-ass syntax checker. the CONSTANT declaration must be after
> > ARCHITECTURE
>
> > but before the BEGIN
>
> > Doh.
>
> What us VHDL people call "the declarative region". All declarations must
> be in a declarative region. You can declare a constant in a process,
> procedure, function or architecture but it's got to be in front of the
> appropriate "begin".
>
> regards
> Alan
>
> P.S. I know there are other places declarations are allowed but "that's
> not important right now"
>
> --
> Alan Fitch
> Douloshttp://www.doulos.com

I have no problem with that, only that the syntax checker could of
told me that:

"error:xyz: constant declaration not allowed in concurrent block. "

instead of sending me on a wild goose chase about "type"

Hi,

I just had the same problem and it has disappeared after I have moved
the constants just after the "signal" statements (several lines
higher, before "begin" statement) and specified the type of the
constant as following:

constant system_clock_period :TIME := 10ns;

Looks like a bug in ISE... I have 10.1. Downloading Service Pack 3
now, will see if it solve the problem permanently.

Cheers,
Alex