FPGA Central

Has anyone investigated implementimg neural nets in FPGAs?

No, no-one has. That's why when you put 'neural nets fpga' into Google, you
get no hits whatsoever. Apart from the first 10000, that is.
Syms.
"e" <[email protected]> wrote in message
news:[email protected]..
> Has anyone investigated implementimg neural nets in FPGAs?

On Sat, 9 Apr 2005 18:17:18 -0700, "Symon" <[email protected]>
wrote:

>No, no-one has. That's why when you put 'neural nets fpga' into Google, you
>get no hits whatsoever. Apart from the first 10000, that is.
>Syms.


More importantly, has anybody found a use for neural nets?

John

"John Larkin" <[email protected]> wrote in message
news:[email protected]..
> On Sat, 9 Apr 2005 18:17:18 -0700, "Symon" <[email protected]>
> wrote:
>
>>No, no-one has. That's why when you put 'neural nets fpga' into Google,
>>you
>>get no hits whatsoever. Apart from the first 10000, that is.
>>Syms.
>
>
> More importantly, has anybody found a use for neural nets?
>
> John
>
>
I use mine daily....

Tryin to avoid some gardening work I had to check that out.

I only see upto p76 so 760 of 9880 refs.

Even after turning off a redundancy warning it goes to 980 out of 11600
so I guess the other 9-10k can't be reached or can they?

Is it possible to random access out there in the 9880 boonies, I don't
usually go further than 1st few pages. And google says it won't go past
1000. Hint directly type in over "num=300" to jump but 1000 gate still
there.

Anyway to save the whole thing to file in 1 go?
(after change settings to 100 items per page)


johnjakson at usa dot com

On Sat, 09 Apr 2005 22:21:59 -0700, John Larkin
<[email protected]> wrote:

>On Sat, 9 Apr 2005 18:17:18 -0700, "Symon" <[email protected]>
>wrote:
>
>>No, no-one has. That's why when you put 'neural nets fpga' into Google, you
>>get no hits whatsoever. Apart from the first 10000, that is.
>>Syms.
>
>
>More importantly, has anybody found a use for neural nets?
>
>John
>

Yes,

I've very likely that the letter you receive are sorted by zip code
using a neural nets. That's only one example in a million others

Nick

OK -
Let me rephrase my question.

Has anyone who frequents this newsgroups and has a lot of experience
with FPGAs, actually tried to make a functioning NN system and has some
realworld experience with FPGA NN Systems.
(Mean as it may sound , this is meant to rule out present or past
graduate students that only got as far simulation.)




JJ wrote:
> Tryin to avoid some gardening work I had to check that out.
>
> I only see upto p76 so 760 of 9880 refs.
>
> Even after turning off a redundancy warning it goes to 980 out of 11600
> so I guess the other 9-10k can't be reached or can they?
>
> Is it possible to random access out there in the 9880 boonies, I don't
> usually go further than 1st few pages. And google says it won't go past
> 1000. Hint directly type in over "num=300" to jump but 1000 gate still
> there.
>
> Anyway to save the whole thing to file in 1 go?
> (after change settings to 100 items per page)
>
>
> johnjakson at usa dot com
>

More likely than not, most regulars here probably have not dipped their
finger into NNs as they are probably busy more in DSP, or embedded
space.

But google fpga neural networks on the web did highlight at least a
couple of may be interesting articles for you to start with. Those
authors may or may not have been here too but AFAIK I haven't seen NN
come up that often.

google groups too to see where they hang out

regards

johnjakson

e wrote:
> Has anyone investigated implementimg neural nets in FPGAs?

Many (most?) classical neural networks utilise non-linear functions at
the nodes, with fractional synapse weights and so on. In SW
implementations, floating point is the order of the day.

Add in the back-propagation training algorithms and you have significant
non-integer arithmetic to contend with.

For implementation in commodity FPGA HW, this will all hurt. Fixed
point will help, but bring similar precision issues that arise in DSP.

Perhaps there is research on pure digital neural networks (binary
weights, logical and/or/xor node functions) etc? Dig around in the
evolvable hardware research literature, they've been banging on it for
years.

It is my expectation (not experience), that there will be significant
practical issues in implementing reasonable sized classical NNs on FPGA
hardware. You will very quickly find yourself building either huge
arrays of FPGAs, or diving into dynamic reconfig / multicontext FPGA
territory to get the logic coverage required to implement what will be a
very large (virtual) circuit.

Or, implement a couple of NN nodes in your FPGA fabric, with some sort
of controller updating the weights and accumulating responses at each
node. Use this to simulate the entire massive (and parallel) NN operation.

Surprise surprise it's time/area trade.

Lots of fun no doubt, but not trivial either.

John

Take a look at GenoByte, http://www.genobyte.com/cbm.html.

News is old though, ca. 2000.

-- Pete

e wrote:
> Has anyone investigated implementimg neural nets in FPGAs?

I have a PhD student (Jihan Zhu) working in this area. There have been many
implementations of NN's in FPGAs over the years. The first seems to have
been
Cox, C.E. and E. Blanz, GangLion - a fast field-programmable gate array
implementation of a connectionist classifier. IEEE Journal of Solid-State
Circuits, 1992. 28(3): p. 288-299.

A very brief (4 page) survey appeared in FPL in 2003:
J. Zhu and P. Sutton, "FPGA Implementations of Neural Networks - a Survey of
a Decade of Progress," in Proceedings of 13th International Conference on
Field Programmable Logic and Applications (FPL 2003), Lisbon, Sep 2003.

It's online at
http://www.itee.uq.edu.au/~peters/pa...on_fpl2003.pdf

Peter

"Peter Sommerfeld" <[email protected]> wrote in message
news:[email protected] oups.com...
> Take a look at GenoByte, http://www.genobyte.com/cbm.html.
>
> News is old though, ca. 2000.
>
> -- Pete
>
> e wrote:
>> Has anyone investigated implementimg neural nets in FPGAs?
>

e wrote:

> Has anyone investigated implementimg neural nets in FPGAs?

I saw a paper maybe 10 years ago on a neural net set up in an FPGA
(small by todays standards), It used bit serial arithmetic and was able
to fit more nodes than one might have thought. IIRC, this was an early
xilinx 4K family.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email [email protected]
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

You might google "Federico Faggin" (my boss at Zilog 26 years ago) or
Synaptics, his later company...
Peter Alfke