FPGA Central

Hi all,
I have a design which has 15 blocks.
Data enters from 1st block and after 60 clocks comes out from 15th
block.
I control enabling of each block by using a counter which counts till
60 at each clock (same clock as above).
So this counter output(say count) goes to every block and every block
has statements something like this :

Blcok 1:
If count >=2 than
-----Do something
end if;

Blcok 2:
If count >=4 than
-----Do something
end if;

Blcok 3:
If count >=7 than
-----Do something
end if;

Blcok 4:
If count >=18 than
-----Do something
end if;

................and so on.

Blcok 15:
If count >=18 than
-----Do something
end if;


My question is that is the data going in block 1 and being processed
through all the blocks and than coming out of block 15 will be a
Multi-Cycle path ?
And why ?


Thanks
Ved

Ved wrote:
> Hi all,
> I have a design which has 15 blocks.
> Data enters from 1st block and after 60 clocks comes out from 15th
> block.
> I control enabling of each block by using a counter which counts till
> 60 at each clock (same clock as above).
> So this counter output(say count) goes to every block and every block
> has statements something like this :
>
> Blcok 1:
> If count >=2 than
> -----Do something
> end if;
>
> Blcok 2:
> If count >=4 than
> -----Do something
> end if;
>
> Blcok 3:
> If count >=7 than
> -----Do something
> end if;
>
> Blcok 4:
> If count >=18 than
> -----Do something
> end if;
>
> ...............and so on.
>
> Blcok 15:
> If count >=18 than
> -----Do something
> end if;
>
>
> My question is that is the data going in block 1 and being processed
> through all the blocks and than coming out of block 15 will be a
> Multi-Cycle path ?
> And why ?
>
>
> Thanks
> Ved

You don't show any data flow in the pseudo code, but in general
the definition of a multicycle path is when the output of a flip-flop
is not sampled on the next active edge of the clock after the
signal changes. This would occur for example if data that only
transitions while "count" is odd is only sampled while "count"
is odd. In this case there would always be 2 clock cycles
for data to settle after changing before it is sampled.

Also I'm not sure but do you really mean >= (greater or equal)
in your comparisons? This would seem to imply you generally
don't have Multi-Cycle paths, since each block could run
on a number of consecutive clock cycles.

HTH,
Gabor