FPGA Central

Hi to everyone,
I'm using an Actel fuse A54SX72A, which has 2012 sequential cells and at
the moment I filled it up to more than 90%.
There can be the need more triple-redundant registers in it and I'm
afraid I will have routing problems with that.
Has anyone here experienced this? Can I rely on the Actel Designer
backannotate to have a close-to-reality simulation?

Thanks a lot

--
Alessandro Basili
CERN, PH/UGC
Hardware Designer

Hi Alessandro,

> I'm using an Actel fuse A54SX72A, which has 2012 sequential cells and at
> the moment I filled it up to more than 90%.

Once I got it up to 100%! So you still have some cells to spare.

> There can be the need more triple-redundant registers in it and I'm
> afraid I will have routing problems with that.

Routing depends on your design structure. Even with high device
utilization, Designer usually is successful. If routing fails or you
can't get timing closure, you can try place&route with the "Multiple
Passes" option.

> Has anyone here experienced this? Can I rely on the Actel Designer
> backannotate to have a close-to-reality simulation?

Certainly. You can export the netlist together with the SDF to perform
gate-level simulation with effective cell and routing delays.


Daniel Leu
Inicore, Inc.

Hi Daniel,

Daniel Leu wrote:
>
> Routing depends on your design structure. Even with high device
> utilization, Designer usually is successful. If routing fails or you
> can't get timing closure, you can try place&route with the "Multiple
> Passes" option.

I will try it, thanks. Does it have any drawback?
>
> Certainly. You can export the netlist together with the SDF to perform
> gate-level simulation with effective cell and routing delays.
>

I thought that this is what the back-annotate does, am I wrong?
I usually do the back-annotate and then do the post-layout simulation
with Model-Sim (unfortunately by the mean of Libero IDE, that I
personally hate, but still didn't have time to make rid of it).
What do you mean by "gate-level simulation"?

>
> Daniel Leu
> Inicore, Inc.
>

--
Alessandro Basili
CERN, PH/UGC
Hardware Designer

alessandro basili wrote:
> Hi Daniel,
>
> Daniel Leu wrote:
> >
> > Routing depends on your design structure. Even with high device
> > utilization, Designer usually is successful. If routing fails or you
> > can't get timing closure, you can try place&route with the "Multiple
> > Passes" option.
>
> I will try it, thanks. Does it have any drawback?

Longer runtime.

> >
> > Certainly. You can export the netlist together with the SDF to perform
> > gate-level simulation with effective cell and routing delays.
> >
>
> I thought that this is what the back-annotate does, am I wrong?
> I usually do the back-annotate and then do the post-layout simulation
> with Model-Sim (unfortunately by the mean of Libero IDE, that I
> personally hate, but still didn't have time to make rid of it).
> What do you mean by "gate-level simulation"?

Yes, this is what I meant. You should be able to run the back-annotated
with Modelsim without Libero.

Regards,
Daniel Leu
Inicore, Inc.

Hi,

alessandro basili schrieb:
> Daniel Leu wrote:
> >
> > Routing depends on your design structure. Even with high device
> > utilization, Designer usually is successful. If routing fails or you
> > can't get timing closure, you can try place&route with the "Multiple
> > Passes" option.
>
> I will try it, thanks. Does it have any drawback?

It cost only time by doing effectly several runs and using the best
result (you could even have the results from all runs saved on HD)
I think, that timing critical layout gets a bigger problem if your
utilisation is >>95% (YMMV I had only one A54SX72 design exceeding 95%
sequential resources).

> I thought that this is what the back-annotate does, am I wrong?
> I usually do the back-annotate and then do the post-layout simulation
> with Model-Sim (unfortunately by the mean of Libero IDE, that I
> personally hate, but still didn't have time to make rid of it).
> What do you mean by "gate-level simulation"?

I never used the IDE, what causes your pain? The export of netlist and
sdf from designer tool is very simple (I wish all Vendors would allow
such a simple export of data in their tools).

bye Thomas

Thomas Stanka wrote:
> Hi,
> It cost only time by doing effectly several runs and using the best
> result (you could even have the results from all runs saved on HD)
> I think, that timing critical layout gets a bigger problem if your
> utilisation is >>95% (YMMV I had only one A54SX72 design exceeding 95%
> sequential resources).
>

To be more precise it only takes more than 90% of the sequential logic,
so that's why I'm not yet having any trouble, because I think that the
major problem will occur when you have a lot of combinational logic to
go through.
(By the way, what does YMMV mean???)
>
> I never used the IDE, what causes your pain? The export of netlist and
> sdf from designer tool is very simple (I wish all Vendors would allow
> such a simple export of data in their tools).
>
The Designer is very easy to use and I appreciated it a lot, my only
problem is that all my collegues used to make projects with LIBERO IDE
and I had to adapt myself to their standards. Now I only use Libero to
set up all the directories in such a way I'm used to, but then I use
Synplify by itself and Modelsim as well.
Libero is only handy when it creates the .do script file for Modelsim
and goes through the post-synthesis or the post-layout simulation just
in case you have exported the back-annotate from the Designer.

> bye Thomas
>

--
Alessandro Basili
CERN, PH/UGC
Hardware Designer

Hi,

Al schrieb:

> Thomas Stanka wrote:
> > Hi,
> > It cost only time by doing effectly several runs and using the best
> > result (you could even have the results from all runs saved on HD)
> > I think, that timing critical layout gets a bigger problem if your
> > utilisation is >>95% (YMMV I had only one A54SX72 design exceeding 95%
> > sequential resources).
> >
>
> To be more precise it only takes more than 90% of the sequential logic,
> so that's why I'm not yet having any trouble, because I think that the
> major problem will occur when you have a lot of combinational logic to
> go through.

Both *g*. Of course is the number of gates in a path important for the
timing. But your longest path is very likely dominated by routing
delay. You will typically have some bad routings exceeding the gate
delay of 4-5 gates if your resource usage is high.

Just open layout tool and timing analyiser in parallel to see the
influence of layout on your timing. You will easily see some registers,
that should be moved to improve timing, but high resource usage
disables the possibility to put them close together without worsening
other delays.

> (By the way, what does YMMV mean???)

Your mileage may vary (http://en.wikipedia.org/wiki/YMMV).

bye Thomas