FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 03-04-2004, 08:30 AM
skywave
Guest
 
Posts: n/a
Default Module design:why design can't run in "virtex2"

I have some problems when I am running the modular design flow in Xilinx ISE 5.1i. After entering the top-level design codes and synthesizing them successfully, I enter commands like this"ngdbuild -p xc2v3000-bf957-6 -uc alu.ucf -modular initial alu.ngc alu.ngd", and I get a failed message"can't run ngdbuild in modular design mode for 'virtex2' architecture".I don't know why.
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Xilinx "This design element is inferred rather than instantiated" (newbie) Nevo Verilog 3 07-30-2006 04:58 PM
How in Design Compiler disable writing out "Assign" statement into the netlist? Frank Verilog 2 01-22-2006 05:36 PM
Altera's Quartus II "smart compilation" feature killed my design? enq_semi FPGA 12 09-19-2003 09:06 PM


All times are GMT +1. The time now is 02:51 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2012, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved