FPGA Central

ML 403 evaluation board (Virtex 4)
Xilinx ISE 11.1

Essentially we are trying to a load a simple program onto our FPGA but w
have been having a lot of trouble. We have a simple program with two input
a and b and and output y. We are simply trying to execute y <= a OR b. W
are trying to assign a and b inputs to button switches on the board and th
output y to an LED. We have looked online for the proper pinouts but ar
getting an error after changing the ucf file to match the pinouts poste
online. Can someone please offer a step by step process to load this simpl
program onto the virtex 4?
--------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY orgate IS
PORT ( a : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
y : OUT_STD_LOGIC_VECTOR (1 DOWNTO 0));
END orgate;

ARCHITECTURE orgate1 OF orgate IS
BEGIN
y <= (a OR b);
END orgate1;
---------------------------------------------------
thanks!

glallenjr wrote:
> Can someone please offer a step by step process to load this simple
> program onto the virtex 4?
> --------------------------------------------------
> LIBRARY ieee;
> USE ieee.std_logic_1164.all;
>
> ENTITY orgate IS
> PORT ( a : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
> b : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
> y : OUT_STD_LOGIC_VECTOR (1 DOWNTO 0));
> END orgate;
>
> ARCHITECTURE orgate1 OF orgate IS
> BEGIN
> y <= (a OR b);
> END orgate1;
> ---------------------------------------------------

it's completely buggy : a, b and y are 2-bit vectors ???
and what about the OUT_ : remove the '_'
it's more a VHDL syntax learning problem that is the cause
of those troubles (for now).

> thanks!
well...

--
http://ygdes.com / http://yasep.org

"glallenjr" <[email protected]> writes:

> ML 403 evaluation board (Virtex 4)
> Xilinx ISE 11.1
>
> Essentially we are trying to a load a simple program onto our FPGA but we
> have been having a lot of trouble. We have a simple program with two inputs
> a and b and and output y. We are simply trying to execute y <= a OR b. We
> are trying to assign a and b inputs to button switches on the board and the
> output y to an LED. We have looked online for the proper pinouts but are
> getting an error after changing the ucf file to match the pinouts posted
> online. Can someone please offer a step by step process to load this simple
> program onto the virtex 4?
> --------------------------------------------------
> LIBRARY ieee;
> USE ieee.std_logic_1164.all;
>
> ENTITY orgate IS
> PORT ( a : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
> b : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
> y : OUT_STD_LOGIC_VECTOR (1 DOWNTO 0));
> END orgate;
>
> ARCHITECTURE orgate1 OF orgate IS
> BEGIN
> y <= (a OR b);
> END orgate1;

As has been pointed out, that's not valid VHDL. I suggest you learn to
simulate your design first. You can iterate fixes *much* quicker.

I know it's not as exciting as actually flashing lights, but it really
is the way to go!

As I'm waiting for XPS to compile (yawn), here's a simulator testbench
to get you going.... as I use Emacs vhdl-mode, this took me about 35
secs You'll see there's some bits for you to fill in...


library ieee;
use ieee.std_logic_1164.all;
entity tb_orgate is
end entity tb_orgate;
architecture test of tb_orgate is
signal a : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal b : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal y : STD_LOGIC_VECTOR (1 DOWNTO 0);
begin -- architecture test
DUT: entity work.orgate
port map (
a => a,
b => b,
y => y);
WaveGen_Proc: process
begin
a <= "00";
b <= "00";
wait for 0 ns; -- allow gate to propogate result
assert y="Put the answer you expect in here"
report "answer wrong"
severity error;

wait for 10 ns; -- just so the waveforms progress along the time axis!
a <= "01";
b <= "10";
wait for 0 ns; -- allow gate to propogate result
assert y="Put the answer you expect in here"
report "answer wrong"
severity error;
-- Put some more tests in here with different a and b values
-- for extra credit use a pair of nested loops to test all the combinations of inputs,
-- using VHDL to "calculate" the right answer to put in the assert statement

report (time'image(now) & " Finished");
wait;
end process WaveGen_Proc;
end architecture test;

Cheers,
Martin

--
[email protected]
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html