FPGA Central

Hello,

I have a newbie problem that is probably easy to solve.

I have 4 data streams entering Virtex II FPGA through LVDS standard (each
stream is 4 wires, 2 clock and 2 data). This is fine as I am able to
receive the
signals each individually i.e. data from each stream is clock by only their
respective
clock and the data does not interact with each other.

What I want to do is to treat each stream as a bit of a word i.e. have them
all
clocked by a single clock. Because these streams are independent clock
phases
and probably clock jitter is not equal, though frequency should nominally be
equal.

Is there a way to generate a single clock and/or correct for phase
differences on the
data streams so that can can treat the data as a single "word"? How should
I look
at this problem?

Herwin

On Sun, 8 Feb 2004 22:02:43 -0800, "Herwin" <[email protected]> wrote:

>Hello,
>
>I have a newbie problem that is probably easy to solve.
>
>I have 4 data streams entering Virtex II FPGA through LVDS standard (each
>stream is 4 wires, 2 clock and 2 data). This is fine as I am able to
>receive the
>signals each individually i.e. data from each stream is clock by only their
>respective
>clock and the data does not interact with each other.
>
>What I want to do is to treat each stream as a bit of a word i.e. have them
>all
>clocked by a single clock. Because these streams are independent clock
>phases
>and probably clock jitter is not equal, though frequency should nominally be
>equal.
>
>Is there a way to generate a single clock and/or correct for phase
>differences on the
>data streams so that can can treat the data as a single "word"? How should
>I look
>at this problem?

Does your system meet the following requirements?

1. The average frequency is exactly the same on all four channels.
(You said "nominally equal" but that could mean anything.)

2. You can put an upper limit on the instantaneous phase difference
between channels.

3. Each channel contains a unique data pattern (frame marker, etc.)
that would allow you to work out the phase difference between the
channels.


If so, then I recommend the following:

Have four independent FIFOs. Each FIFO takes its input from one of
the channels. The output of all FIFOs are clocked from the same
source, which would be the input clock on *one* of the FIFOs, or any
other clock with the same frequency (e.g. one of the input clocks that
has been filtered by a PLL).

The FIFO size is determined by the maximum phase difference from #2
(above).

Have a control input on the FIFO that allows you to adjust the depth
(by fiddling the pointers - it doesn't matter if this trashes the data
briefly during the adjustment), and control this such that the frame
markers (from #3, above) line up on the outputs of all four FIFOs.

BTW, this is very common technique. It is done in some variants of
10G Ethernet (that recombine four 3.125Gbps 8B10B streams into one
10Gbps stream).

Regards,
Allan.