FPGA Central

Hi all
I have a clock of 20Mhz on my board and I want Digital clock manager
to generate a clock of 130MHz in my Xilinx Virtex-2 xc2v1000 FPGA.
Now , the problem is that the DCM requires atleast 24Mhz input clock
for proper working. Is there any solution other than changing the
clock on board ??

regards
MH

On 19 Feb 2007 23:22:06 -0800, "mh" <[email protected]> wrote:

>Hi all
>I have a clock of 20Mhz on my board and I want Digital clock manager
>to generate a clock of 130MHz in my Xilinx Virtex-2 xc2v1000 FPGA.
>Now , the problem is that the DCM requires atleast 24Mhz input clock
>for proper working. Is there any solution other than changing the
>clock on board ??
>
>regards
>MH

The limit of 24 MHz applies to the use of DCM as DLL. If your are
going to use it multiply the frquency, then you are using CLKFX as
output and the limits are 1MHz (LF mode) ansd 3 MHZ (HF mode), so you
will have no problems with your design.

Best regards,

Zara

Zara is correct:

When CLKFX is used (by itself), the input clock can be lower than 24 MHz.

Just make sure that you are not using CLK0, 90, 180, 270 nor CLK2X, nor
CLKDV. Do not connect anything to the CLKFB input.

Austin