FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 03-23-2009, 11:28 PM
ed.agunos@gmail.com
Guest
 
Posts: n/a
Default low-power, high capacity data queue design ideas

So I have to design a low-power data queuing system. I've never done a
low power design, so I though I'd come to this newsgroup to solicit a
few ideas.

I'm going to be continuously receiving data at 55KBps. I have to store
a whole days worth of data before I offload the data to another device
which ends up being ~4.8GB. The offload rate is going to be ~6.5MBps.

My initial thinking is to build Cool-Runner or a Spartan-3E to control
an SD-Card. But it's totally open, so I could use Compact Flash, USB
flash key, or even some SDRAM. So with the main constraints being low-
power and ease of implementation, what would you guys suggest.

Thanks in advance.
Reply With Quote
  #2 (permalink)  
Old 03-23-2009, 11:56 PM
Rob Gaddi
Guest
 
Posts: n/a
Default Re: low-power, high capacity data queue design ideas

On Mon, 23 Mar 2009 15:28:32 -0700 (PDT)
ed.agunos@gmail.com wrote:

> So I have to design a low-power data queuing system. I've never done a
> low power design, so I though I'd come to this newsgroup to solicit a
> few ideas.
>
> I'm going to be continuously receiving data at 55KBps. I have to store
> a whole days worth of data before I offload the data to another device
> which ends up being ~4.8GB. The offload rate is going to be ~6.5MBps.
>
> My initial thinking is to build Cool-Runner or a Spartan-3E to control
> an SD-Card. But it's totally open, so I could use Compact Flash, USB
> flash key, or even some SDRAM. So with the main constraints being low-
> power and ease of implementation, what would you guys suggest.
>
> Thanks in advance.


That's a huge amount of data to be holding onto. Neither writing to
flash nor refreshing that much DRAM is going to be particularly power
cheap. What kind (read how compressable) of data are you going to be
dealing with?

Also, as an initial thought, for these sorts of data rates my mind
goes to a microcontroller long before it goes to any kind of PLD. You
might want to ping comp.arch.embedded with this one, too.

--
Rob Gaddi, Highland Technology
Email address is currently out of order
Reply With Quote
  #3 (permalink)  
Old 03-24-2009, 12:11 AM
Symon
Guest
 
Posts: n/a
Default Re: low-power, high capacity data queue design ideas


"Rob Gaddi" <rgaddi@technologyhighland.com> wrote in message
news:20090323155627.000011fd@unknown...
> Also, as an initial thought, for these sorts of data rates my mind
> goes to a microcontroller long before it goes to any kind of PLD.


What he ^^ said!


Reply With Quote
  #4 (permalink)  
Old 03-24-2009, 12:21 AM
John Adair
Guest
 
Posts: n/a
Default Re: low-power, high capacity data queue design ideas

Just to clarify what power budget do you have?

John Adair
Enterpoint Ltd.

On 23 Mar, 22:28, ed.agu...@gmail.com wrote:
> So I have to design a low-power data queuing system. I've never done a
> low power design, so I though I'd come to this newsgroup to solicit a
> few ideas.
>
> I'm going to be continuously receiving data at 55KBps. I have to store
> a whole days worth of data before I offload the data to another device
> which ends up being ~4.8GB. The offload rate is going to be ~6.5MBps.
>
> My initial thinking is to build Cool-Runner or a Spartan-3E to control
> an SD-Card. But it's totally open, so I could use Compact Flash, USB
> flash key, or even some SDRAM. So with the main constraints being low-
> power and ease of implementation, what would you guys suggest.
>
> Thanks in advance.


Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Re: logarithmic power spectra looks ridiculously high Rune Allnor DSP 3 02-06-2009 10:57 PM
logarithmic power spectra looks ridiculously high adamchapman DSP 1 02-06-2009 09:47 PM
DSP Design Ideas for an Undergrad jfrog DSP 4 05-22-2008 05:20 AM
sysace and high capacity CF zcsizmadia@gmail.com FPGA 0 05-07-2007 05:49 PM
Ideas on Divider design Sunita Jain Verilog 2 10-22-2004 07:20 PM


All times are GMT +1. The time now is 02:41 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2010, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved