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I am trying to synthesize a code using ISE which contains a component
fifo the fifo code is the following

-- synopsys translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity ifo is
.....................
...............
end ifo

ARCHITECTURE st of ifo is
..........
.........
end st

-- synopsys translate_on

If I run the above code using ise it doesnt recognize the component at
all. If I remove the line sysnopsys translate_off then it gives me
following error
Library unit VPKG is not available in library UNISIM

any ideas?
Thanks
-D

dhruvakshad@gmail.com wrote:
> I am trying to synthesize a code using ISE which contains a component
> fifo the fifo code is the following
>
> -- synopsys translate_off
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> library UNISIM;
> use UNISIM.VCOMPONENTS.ALL;
> use UNISIM.VPKG.ALL;

Don't use VPKG, and put the translate_off/on only around the unisim
stuff (in this case "synthesis" is a synonym for "synopsys"):

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- synthesis translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- synthesis translate_on