Antti Lukats wrote:
> "ABS" <abhishekbedi@gmail.com> schrieb im Newsbeitrag
> news:1134518668.567217.216410@o13g2000cwo.googlegr oups.com...
> > hi all
> >
> > has anyone got any documents or refferals for 'J Tag Protocol ' , for
> > reconfigurable hardware.
>
> I bet almost anyone here has...
>
> but JTAG primary function is BOUNDARY SCAN and not hardware reconfiguration,
> even though lots (virtually all) current FPGA allow configuration over JTAG
> interface
>
> > i would appreciate if any tutorials or realted links/documents can b
> > passed on .
> > thanks
> > abhishek
> >
>
On the grounds I want to find out if the OP is creatively lazy...
The relevant specifications are:
for pure JTAG (testing) IEEE 11.94.1 - (year) [there are a number of
releases. Most devices comply with the 1994 release]
For In System programmable devices using JTAG
IEEE1536. Note that the 'BSDL' files for ISP specify the 1536
compatibility (See Altera or Xilinx docs)
For testing cores with 'standard' interfaces, such as EJTAG (MIPS) or
such as ARM core access, you would need to search for the specific
information. EJTAG and ARM core JTAG access protocols are published,
but not necessarily free.
Both 1194 and 1536 are published, but not free, although there is a
wealth of available information if you want to learn about it.
Cheers
PeteS
> it takes a few seconds to find those documents by googling for them, if you
> are too lazy for that there is no one who can help you.
>
> Antti
> PS I admire 'creative lazyness' but not people who are just lazy.