FPGA Central

International Journal of High Performance Systems Architecture (IJHPSA)
ISSN (Online): 1751-6536 - ISSN (Print): 1751-6528

http://www.inderscience.com/ijhpsa

Published in 4 issues per year

IJHPSA proposes and fosters discussion on all aspects of the design and
implementation of high-performance architectures, which are centred
around the concept of parallel processing. The journal will cover all
types of advanced architectures ranging from pipelined structures,
array processors and multiprocessor systems. Dedicated high-performance
architectures and systems, as well as hardware and software design
methods and tools, will also fall within the scope of IJHPSA.

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Objectives
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IJHPSA provides a lively forum for the communications of original
research. It acts as a scientific and professional journal to timely
disseminate original research work on advanced systems architecture,
which is at the heart of high-performance and cost-effective systems.

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Readership
==========

The audience for IJHPSA consists of researchers, academics, graduate
students, professionals and system engineers working and interested in
high-performance systems and their underlying advanced architectures.

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Contents
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IJHPSA publishes original peer-reviewed papers, which include research
papers, review papers, case studies, book reviews. Special Issues
devoted to important topics on advanced systems architecture will
occasionally be published.

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Subject Coverage
================

Suitable topics include, but are not limited to:

* Pipelining
Pipelined architectures
Vectorisation methods
Vector processing
Dynamic pipelines
Pipeline chaining
* Array Processors
Interconnections network topologies, such as systolic, mesh, cube,
etc.
Parallel algorithms for array processors
Associative array processors
Masking and routing mechanisms
* Multiprocessor Systems
Multiprocessor architectures
Tightly and loosely-coupled multiprocessors
Interconnection networks
Parallel memory organisation and multi-cache
Multiprocessing control
* RISC Architectures
Instruction set
Pipelined RISC architectures
* Data Flow Systems
Data-driven computing
Data flow architectures
* VLSI Architectures
VLSI computing structures
Dedicated VLSI architectures
* Performance evaluation and new trends

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Specific Notes for Authors
==========================

Submitted papers should not have been previously published nor be
currently under consideration for publication elsewhere. All papers are
refereed through a double blind process. A guide for authors, sample
copies and other relevant information for submitting papers are
available on the Submission of Papers web-page. You may send one copy
in the form of a PDF (preferred) or an MS Word file attached to an
e-mail (details of file formats in Author Guidelines) to Nadia Nedjah,
below, with an email copy only to:

IEL Editorial Office
E-mail: [email protected]

Please include in your submission the title of the Journal

===============
Editorial Board
===============

Editor-in-chief

Dr. Nadia Nedjah [email protected]
http://www.eng.uerj.br/~nadia/english.html

Editorial Board Members

Dr. Enrique Alba
Dr. Nader Bagherzadeh
Dr. Moreshwar R Bhujade
Dr. Felipe M. G. França
Dr. Fabrizio Gagliardi
Dr. Paul H. J. Kelly
Dr. Antonio C. Mesquita
Dr. Luiza de Macedo Mourelle
Dr. Alberto Prieto
Dr. Stanislav G. Sedukhin
Dr. Arnaud Tisserand
Dr. Pedro Trancoso
Dr. Augustus K. Uht
Dr. Mateo Valero
Dr. Cheng-Zhong Xu
Dr. Mei Yang
Dr. Jurij Silc