FPGA Central

I registered a 37-bit signal using an always block in verilog without
reset specification, hoping that a SRL would be inferred if registering
is done without a reset. But ISE still implemented it as a 37-bit
register using flops. Could anyone please let me know if I missed out
something? Any comments/suggestions would be appreciated. Thanks in
advance.

Hi Rohit,

"Rohit Tandon" <rohit2000s@gmail.com> wrote in message
news:[email protected] oups.com...
> I registered a 37-bit signal using an always block in verilog without
> reset specification, hoping that a SRL would be inferred if registering
> is done without a reset. But ISE still implemented it as a 37-bit
> register using flops. Could anyone please let me know if I missed out
> something? Any comments/suggestions would be appreciated. Thanks in
> advance.

The conditions for SRL16 inference for are:

(1) No resets (which you've covered);
(2) Identical clock-enables for all registers, or no clock-enables;
(3) Output of stage N feeds input of stage N+1 with no intervening logic;
(4) Output of each stage does not feed any other destination

For example, if you want a parallel-in, serial-out shift register (or
serial-in, parallel-out) then you cannot use SRL16s. Make sure all the
conditions above are met by your circuit.

Also check that SRL16 inference is enabled in your synthesis tool's options
(in your case XST, I guess).

If it still doesn't work, perhaps you could post the code for us to look at?

Cheers,

-Ben-

Rohit Tandon wrote:
> I registered a 37-bit signal using an always block in verilog without
> reset specification, hoping that a SRL would be inferred if registering
> is done without a reset. But ISE still implemented it as a 37-bit
> register using flops. Could anyone please let me know if I missed out
> something? Any comments/suggestions would be appreciated. Thanks in
> advance.

Howdy Rohit,

SRL inferrance usually works, so to actually be of much help, we need
to know:

1. What synthesis program you're using (XST? Synplify?)
2. What code you are using for the SRL inferrance (copy and paste a
simplified always block that you are trying to use)

Good luck,

Marc

Ben Jones wrote:
> Hi Rohit,
>
> "Rohit Tandon" <[email protected]> wrote in message
> news:[email protected] oups.com...
> > I registered a 37-bit signal using an always block in verilog without
> > reset specification, hoping that a SRL would be inferred if registering
> > is done without a reset. But ISE still implemented it as a 37-bit
> > register using flops. Could anyone please let me know if I missed out
> > something? Any comments/suggestions would be appreciated. Thanks in
> > advance.
>
> The conditions for SRL16 inference for are:
>
> (1) No resets (which you've covered);
> (2) Identical clock-enables for all registers, or no clock-enables;
> (3) Output of stage N feeds input of stage N+1 with no intervening logic;
> (4) Output of each stage does not feed any other destination
>
> For example, if you want a parallel-in, serial-out shift register (or
> serial-in, parallel-out) then you cannot use SRL16s. Make sure all the
> conditions above are met by your circuit.
>
> Also check that SRL16 inference is enabled in your synthesis tool's options
> (in your case XST, I guess).
>
> If it still doesn't work, perhaps you could post the code for us to look at?
>
> Cheers,
>
> -Ben-

Thanks to both of you for your quick replies. Actually I was using
output of one stage of the shift register in the logic elsewhere in the
design, when I modified it, XST was infering a SRL (without the need
for XST SRL tool option).

I was wondering if a similar solution can be applied to another problem
where I need to just add some 2-cycles of delay to a 4-bit register.
For instance if I have something like this:

reg [3:0] reg_in ;
reg [3:0] reg_out ;
reg [3:0] reg_r1 ;

always @ (posedge clk)
begin
{reg_out, reg_r1} <= {reg_r1, reg_in} ;
end

Can this logic be modified to make use of SRLs or do I need to
invariably implement it via flops.

Thanks in advance
-Rohit

Rohit Tandon wrote:
[...]
> Thanks to both of you for your quick replies. Actually I was using
> output of one stage of the shift register in the logic elsewhere in the
> design, when I modified it, XST was infering a SRL (without the need
> for XST SRL tool option).
>
> I was wondering if a similar solution can be applied to another problem
> where I need to just add some 2-cycles of delay to a 4-bit register.
> For instance if I have something like this:
>
> reg [3:0] reg_in ;
> reg [3:0] reg_out ;
> reg [3:0] reg_r1 ;
>
> always @ (posedge clk)
> begin
> {reg_out, reg_r1} <= {reg_r1, reg_in} ;
> end
>
> Can this logic be modified to make use of SRLs or do I need to
> invariably implement it via flops.

Howdy Rohit,

Unless it is somehow broken in the version of XST that you are using,
it should be possible with the correct syntax. You'll have to look it
up the SRL template for Verilog in XST. A complete WAG: maybe start by
breaking the reg_out portion of your statement to a separate line.

Have fun,

Marc

Hi Rohit,

"Rohit Tandon" <[email protected]> wrote in message
news:[email protected] oups.com...
>
> I was wondering if a similar solution can be applied to another problem
> where I need to just add some 2-cycles of delay to a 4-bit register.
> For instance if I have something like this:
>
> reg [3:0] reg_in ;
> reg [3:0] reg_out ;
> reg [3:0] reg_r1 ;
>
> always @ (posedge clk)
> begin
> {reg_out, reg_r1} <= {reg_r1, reg_in} ;
> end
>
> Can this logic be modified to make use of SRLs or do I need to
> invariably implement it via flops.

I'm no Verilog expert, but that looks like it should work without
modification. Certainly there should be no need for the delay-line signals
to have related names or be in elements of the same array for the tool to
detect a shift register.

However, you may find that XST will not bother to use SRL16s for such a
short delay line. In that case you might find you need to instantiate them
if you really really want them.

Cheers,

-Ben-