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Dear

Asking many questions on this board --:

My goal is to get "critical path delay" (or maximum clock frequency)
of simple "register file", as described in the following :

---------------------------
There is a register.
Before register, there is a combinational logic.
After register, there is a combinational logic.
---------------------------

I obtained following 5 different reports.
My question is that which report (ouf of (1),(2),(3a),(3b),(3c) )
represents the most accurate "critical path delay" of my
implementation?

(1) Synthesis report reports :
---------------------------
Minimum period: No path found
Minimum input arrival time before clock: 4.026ns
Maximum output required time after clock: 4.636ns
Maximum combinational path delay: 5.975ns
---------------------------

(2) Asynchronous delay report reports :
---------------------------
The 20 worst nets by delay are:
| Max Delay | Netname |
9.579 ReadRegister1_0_IBUF
8.965 SelectRC_IBUF
8.524 ReadRegister2_0_IBUF
........
---------------------------

(3) Post Place & Route Static Timing report reports :
---------------------------
(3a)Pad to Pad
--------------------------
Source Pad |Destination Pad| Delay |
ReadRegister1<0>|ReadData1<0> | 10.063|
ReadRegister1<0>|ReadData1<1> | 12.041|
....

---------------------------
(3b) Clock clock to Pad
---------------------------
| clock
| | clock |
Destination | to PAD |Internal Clock(s) | Phase |
ReadData1<0> | 9.365(R)|clock_BUFGP | 0.000|
ReadData1<1> | 9.557(R)|clock_BUFGP | 0.000|
ReadData1<2> | 9.465(R)|clock_BUFGP | 0.000|
.........
---------------------------
(3c) Setup/Hold to clock clock
---------------------------
| Setup to | Hold to |
| Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) |
Phase |
SelectRC | 13.663(R)| -1.584(R)|clock_BUFGP |
0.000|
WriteData<0> | 3.373(R)| -0.104(R)|clock_BUFGP |
0.000|
WriteData<1> | 2.466(R)| 0.711(R)|clock_BUFGP |
0.000|
.........