FPGA Central

Dear

I need some comments on managing the 'global reset' in ISE6.3(XST) from
experienced one.

I am post-placement-and-routing simulating in Modelsim. This module has
input reset port. During synthesis/mapping, there is no warning/error.

During the simulation, followings are observed, which are maybe or
maybe not be problematic.

- In behavioral simulation, it works, even though no value is assigned
to reset signal in test vector.

- After placement-and-routing simulation, it works, only when we put
reset signal is '0' in test vector.

I am wondering if this is problematic.

I have found that when reset behaves differently in simulation than in
PAR it usually points to the global reset path been gated. Generally
you should treat reset signals with almost the same care you treat Clk
signals (most importantly by not gating them).

Try also passing the reset signal through an BUF or even edge detecting
it to ensure that it is stable. (remember that most reset signals come
from outside pins and can have wild fluctuations before settling).
Generally, behavioral simulations assume ideal signals.

Hope this helps.

Robin