FPGA Central

Using ISE webpack 10.1.02 running under linux.

I am integrating a set of previously written design blocks into a higher
level of the design. The top level is instruction_decode. Some time ago
I enabled saving files hierarchically by ticking Generate Multiple
Hierarchical Netlist Files button in the Generate Post-Synthesis
Simulation Model process. This worked quite well for some time.

I corrected the name of the block within the file (to make it the same
as the filename). I ended up with two entries in the library. I was
deleting this and probably did something else wrong. At the moment I
cannot turn on multiple hierarchical netlist files without using the tcl
interface.

When I use the tcl interface I use the following commands I can turn on
multiple hierarchical netlist files.
project set "Keep Hierarchy" "Yes" -process "Synthesize - XST"
project set "Generate Multiple Hierarchical Netlist Files" "True"
Whilst this works and gives me the correct number of files I get
warnings of the form:-
WARNING:NetListWriters:306 - Signal bus add_0[56 : 8] on block multiply
is not
reconstructed, because there are some missing bus signals.

( That design block on its own synthesise cleanly.)

If I do a flat synthesis run. i.e. no sub modules at all. No synthesis
warnings are given. There is only one design block in the one file.
There are 4 design blocks.

AR #17693 describes some methods for ISE 6.1 . However some of the
options do not exist in 10.1.

Using a previous snapshot does not restore the ultiple hierarchical
netlist files setting.

What I would like to know is to restore *all* of the defaults. Then I
can enable multiple hierarchical netlist files.

Are there any more modern explanations available e.g. for webpack 10.1?

How can I save settings like this (somewhere else) so that I can restore
them easily?

Apologies for such a long post I am running out of ideas. Andy B