FPGA Central

After some search on this group, at the internet and at Xilinx web
site I have not found a conclusive set of informations regarding the
behavior of a Spartan-3's input pin in a high voltage signaling.
The circuit would use a 27Kohm series resistor to sense the presence
of a 24V signal. It is a very slow signal and the series limiting
resistor would use the ESD clamp diodes to keep the input voltage
below the gate oxide limits. The 27K values was chosen to have the
zero state input with maximum leakage current for this device (25uA).
I understand the 10mA limit on the clamp diodes (100mA max for this
device) would not be stressed with the near 1mA current flow but I
wonder if this situation could somehow reduce the part's MTBF and in
which amount.
I'd like to avoid using an external diode to VCCO (or a zener also
because it's knee) since any other part in the system will reduce the
overall MTBF.
In case it is important there will be 56 inputs in this condition in a
TQ144 package.

Using the help of this group I would like to include here another
question: many documents at Xilinx says the clamp diodes are not
present when the pin is configured as outputs. Is the electronic
structure of these pins with such level of complexity that can avoid
the parasitic diodes (a natural feature for a CMOS architecture)? The
XAPP429 and device's data sheet also suggest the input pin structure
for CoolRunner-II devices doesn't have clamp diode to VCCO. How can it
deal with ESD without the diode to VCCO?

Thanks in advance for your help in this matter.
-Augusto

AugustoEinsfeldt wrote:
> After some search on this group, at the internet and at Xilinx web
> site I have not found a conclusive set of informations regarding the
> behavior of a Spartan-3's input pin in a high voltage signaling.
> The circuit would use a 27Kohm series resistor to sense the presence
> of a 24V signal. It is a very slow signal and the series limiting
> resistor would use the ESD clamp diodes to keep the input voltage
> below the gate oxide limits. The 27K values was chosen to have the
> zero state input with maximum leakage current for this device (25uA).
> I understand the 10mA limit on the clamp diodes (100mA max for this
> device) would not be stressed with the near 1mA current flow but I
> wonder if this situation could somehow reduce the part's MTBF and in
> which amount.
> I'd like to avoid using an external diode to VCCO (or a zener also
> because it's knee) since any other part in the system will reduce the
> overall MTBF.

What about a resistor to GND ? - that will improve the noise immunity,
as right now you are sensing very close to 1V, whilst 12V is better
sense level for a 24V industrial type signal.


> In case it is important there will be 56 inputs in this condition in a
> TQ144 package.

That's ~56mA of injection current - some devices have MAX limits on
the alowable total injection.
What else is the device doing ?

Slow edges are also not great direct into a FPGA - how slow is very slow ?.

>
> Using the help of this group I would like to include here another
> question: many documents at Xilinx says the clamp diodes are not
> present when the pin is configured as outputs. Is the electronic
> structure of these pins with such level of complexity that can avoid
> the parasitic diodes (a natural feature for a CMOS architecture)? The
> XAPP429 and device's data sheet also suggest the input pin structure
> for CoolRunner-II devices doesn't have clamp diode to VCCO. How can it
> deal with ESD without the diode to VCCO?

The N FET avalanches, typically between 5 & 6V, and the energy is
absorbed that way.

-jg

On Jul 2, 9:34 pm, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:
> AugustoEinsfeldt wrote:
> > After some search on this group, at the internet and at Xilinx web
> > site I have not found a conclusive set of informations regarding the
> > behavior of a Spartan-3's input pin in a high voltage signaling.
> > The circuit would use a 27Kohm series resistor to sense the presence
> > of a 24V signal. It is a very slow signal and the series limiting
> > resistor would use the ESD clamp diodes to keep the input voltage
> > below the gate oxide limits. The 27K values was chosen to have the
> > zero state input with maximum leakage current for this device (25uA).
> > I understand the 10mA limit on the clamp diodes (100mA max for this
> > device) would not be stressed with the near 1mA current flow but I
> > wonder if this situation could somehow reduce the part's MTBF and in
> > which amount.
> > I'd like to avoid using an external diode to VCCO (or a zener also
> > because it's knee) since any other part in the system will reduce the
> > overall MTBF.
>
> What about a resistor to GND ? - that will improve the noise immunity,
> as right now you are sensing very close to 1V, whilst 12V is better
> sense level for a 24V industrial type signal.
>
> > In case it is important there will be 56 inputs in this condition in a
> > TQ144 package.
>
> That's ~56mA of injection current - some devices have MAX limits on
> the alowable total injection.
> What else is the device doing ?
>
> Slow edges are also not great direct into a FPGA - how slow is very slow ?.
>
>
>
I agree with Jim. Add a 3.3 or 3.9 kilohm transistor from each FPGA
pin to ground.
You get much better noise immunity and avoid all the (imaginary) diode
current issues.
Resistors are cheap, small, and very reliable...
Peter Alfke
======================
> > Using the help of this group I would like to include here another
> > question: many documents at Xilinx says the clamp diodes are not
> > present when the pin is configured as outputs. Is the electronic
> > structure of these pins with such level of complexity that can avoid
> > the parasitic diodes (a natural feature for a CMOS architecture)? The
> > XAPP429 and device's data sheet also suggest the input pin structure
> > for CoolRunner-II devices doesn't have clamp diode to VCCO. How can it
> > deal with ESD without the diode to VCCO?
>
> The N FET avalanches, typically between 5 & 6V, and the energy is
> absorbed that way.
>
> -jg

Jim Granville wrote:
>> In case it is important there will be 56 inputs in this condition in a
>> TQ144 package.
>
>
> That's ~56mA of injection current - some devices have MAX limits on
> the alowable total injection.

Another caution for this situation - is to watch the IccIO of the FPGA
does not fall below ~56mA - if it does, you will need a SINKING
regulator, to avoid the supply rails being pulled up - IF the VccIO
pulls high, that WILL do serious things to your MTBF!

For Source/Sinking regulators, look at DDR Termination regulators.
-jg

AugustoEinsfeldt <[email protected]> wrote:
> After some search on this group, at the internet and at Xilinx web
> site I have not found a conclusive set of informations regarding the
> behavior of a Spartan-3's input pin in a high voltage signaling.
> The circuit would use a 27Kohm series resistor to sense the presence
> of a 24V signal. It is a very slow signal and the series limiting
> resistor would use the ESD clamp diodes to keep the input voltage
> below the gate oxide limits. The 27K values was chosen to have the
> zero state input with maximum leakage current for this device (25uA).
> I understand the 10mA limit on the clamp diodes (100mA max for this
> device) would not be stressed with the near 1mA current flow but I
> wonder if this situation could somehow reduce the part's MTBF and in
> which amount.
> I'd like to avoid using an external diode to VCCO (or a zener also
> because it's knee) since any other part in the system will reduce the
> overall MTBF.
> In case it is important there will be 56 inputs in this condition in a
> TQ144 package.

Reconsider using some external buffer, with 5 Volt tolerant inputs. Those
buffers have Z-Diodes to limit the voltage and will direct the current to
ground. And in case anything goes wrong, it's much easier to resolder the
buffer then to resolder the FPGA. If you use Schmitt Trigger Buffer, things
will be saver anyways.

Been there, done that. 24 Volt supply next to some logic line on a
bus. Probe on the logic output. Some wrong move and: Bang: All CPLDs in the
cards have that line fried by the 24 Volt applied accidently. And what's
worse, the charge of PCB boards has thermal copper delamination when
resoldered. Argh.

By the way, does anybody know of a 5-Volt tolerant Schmitt Trigger Buffer
with many inputs. The best I could find are the 2-Gate 74LVC2G14 and
74LVC2G17. Even normal Schmitt-Trigger Multigates are not to find

--
Uwe Bonnes [email protected]

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

>Another caution for this situation - is to watch the IccIO of the FPGA
>does not fall below ~56mA - if it does, you will need a SINKING
>regulator, to avoid the supply rails being pulled up - IF the VccIO
>pulls high, that WILL do serious things to your MTBF!

I recall doing evil things to an Nokia 80286 machine. Shorting 5V & 12V while
running did nothing. But shorting 5V to 12V killed the keyboard controller
such that it failed to reboot

AugustoEinsfeldt <[email protected]> wrote:
>After some search on this group, at the internet and at Xilinx web
>site I have not found a conclusive set of informations regarding the
>behavior of a Spartan-3's input pin in a high voltage signaling.
>The circuit would use a 27Kohm series resistor to sense the presence
>of a 24V signal. It is a very slow signal and the series limiting

How slow signal?

Uwe Bonnes wrote:
> By the way, does anybody know of a 5-Volt tolerant Schmitt Trigger Buffer
> with many inputs. The best I could find are the 2-Gate 74LVC2G14 and
> 74LVC2G17. Even normal Schmitt-Trigger Multigates are not to find

The LVC14 is 6, in SO14 and smaller DFN14 etc, but they are inverting.
Then there are HC7014/HC7541 for Hex/Oct Non Inv, and HC9115, for 9 way
NonInv

Or devices like the Philips LVC244 (and LVC2244) have Schmitt IPs, and
will do 5V IP with lower Vcc.

-jg

Jim Granville <[email protected]> wrote:
> Uwe Bonnes wrote:
> > By the way, does anybody know of a 5-Volt tolerant Schmitt Trigger Buffer
> > with many inputs. The best I could find are the 2-Gate 74LVC2G14 and
> > 74LVC2G17. Even normal Schmitt-Trigger Multigates are not to find

> The LVC14 is 6, in SO14 and smaller DFN14 etc, but they are inverting.
> Then there are HC7014/HC7541 for Hex/Oct Non Inv, and HC9115, for 9 way
> NonInv

> Or devices like the Philips LVC244 (and LVC2244) have Schmitt IPs, and
> will do 5V IP with lower Vcc.

I did the mistake to only look at the TI SN74LVC244A. It neither states
"hysteresis" nor "Schmitt trigger". Their Logic selction guide also only
mentions "Schmitt Trigger" for the 14/17 and some similar device.

The NXP datasheet mentions "Schmitt trigger" but doesn't specify a
hysteresis. But at least it mentions the Schmitt trigger.

At about 0.38 E for single pieces of th NXP 244A, the original poster should
consider ...

Thanks

--
Uwe Bonnes [email protected]

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

On 3 Jul., 12:45, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de>
wrote:

> I did the mistake to only look at the TI SN74LVC244A. It neither states
> "hysteresis" nor "Schmitt trigger". Their Logic selction guide also only
> mentions "Schmitt Trigger" for the 14/17 and some similar device.
>
> The NXP datasheet mentions "Schmitt trigger" but doesn't specify a
> hysteresis. But at least it mentions the Schmitt trigger.

You can add hysteresis to any non inverting buffer with two
resistors.

Kolja Sulimma

Thanks for all responses. Because the time zone I was unable to reply
earlier.
The device will do a lot of slow timings (1 second to 10 minutes),
read 6 serial interface ADC converters (with 2.5MHz SCLK) and talk to
a CPLD (used as port expander and watchdog) at 10Mbps data rate. It is
a 3S200 and may have up to 70% of resources used.

I may stick to the pull-down resistor idea because the system MTBF.
Resistors cause less impact here.
System has a XPLA3 CPLD and other circuits at 3V3 (that is supplied
by a TDK's DC-DC converter) and I think the excess of current will
sink easily. But I will calculate it again. TDK's never answered about
sink capability of their DC-DC modules and I'd like to avoid using a
3V6 zener to do not waste energy in some temperature conditions.
The signal's rise/fall time are around 50us (worst case). I know it is
very slow for this device and I will have some extra current in the
pin's input circuitry but the cycle time of each signal is in the
range of several minutes. So the impact of slow signal transition may
not be important for the system. Only 2 to 5 signals of 56 may change
at same time and since they came from mechanical feedback it is very
unlikely they will really change precisely together.
The design did use schmitt-trigger devices for the inputs in the past
but the MTBF did fall because other added circuits and I thought I
could work out the bounce and slow edges with some sample/timing logic
in the FPGA.

Each of these input signals has a transient suppressor and another
100ohm resistor to the input connector. Those are to protect against
huge ESD strikes and EMC/EMI.

Exercising a bit longer in this subject, in case I can sink externally
(to the FPGA) the excess of current (56mA) and since each clamp diode
for this device can handle 100mA (according DS099), which leads a good
current injection handling, the single input resistor (no pull-down)
could work. I am in the limit of system MTBF and it is why I still
thinking to avoid any other component... The main question remains:
would the FPGA's MTBF be reduced because this current flowing in the
clamp diodes?

System cost is not a big issue but I'd like to avoid high reliability
resistors because availability and lead times. While writing this text
I am having second thoughts about avoiding these resistors... but your
opinion would help in the FPGA's MTBF.

Thanks a lot.
-Augusto

On Jul 3, 8:02 am, AugustoEinsfeldt <a...@terra.com.br> wrote:

> I may stick to the pull-down resistor idea because the system MTBF.
> Resistors cause less impact here.

My concern with the pulldown resistors would be, what if one of them
doesn't effectively installed (open)? The board will probably work
just fine. But now the protection diode will be taking all the
current. If that's okay, fine - but if it's not, presumably the worry
that caused you to put the resistors there in the first place, then
you have a board that might fail early.

On 3 Jul., 15:24, cs_post...@hotmail.com wrote:
> On Jul 3, 8:02 am, AugustoEinsfeldt <a...@terra.com.br> wrote:
>
> > I may stick to the pull-down resistor idea because the system MTBF.
> > Resistors cause less impact here.
>
> My concern with the pulldown resistors would be, what if one of them
> doesn't effectively installed (open)? The board will probably work
> just fine. But now the protection diode will be taking all the
> current. If that's okay, fine - but if it's not, presumably the worry
> that caused you to put the resistors there in the first place, then
> you have a board that might fail early.

So use a number of resistors in parallel and include the voltage at
these nodes
into the production test procedure.

Kolja

On Jul 3, 11:12 am, "comp.arch.fpga" <ksuli...@googlemail.com> wrote:
> On 3 Jul., 15:24, cs_post...@hotmail.com wrote:
>
> > On Jul 3, 8:02 am, AugustoEinsfeldt <a...@terra.com.br> wrote:
>
> > > I may stick to the pull-down resistor idea because the system MTBF.
> > > Resistors cause less impact here.
>
> > My concern with the pulldown resistors would be, what if one of them
> > doesn't effectively installed (open)? The board will probably work
> > just fine. But now the protection diode will be taking all the
> > current. If that's okay, fine - but if it's not, presumably the worry
> > that caused you to put the resistors there in the first place, then
> > you have a board that might fail early.
>
> So use a number of resistors in parallel and include the voltage at
> these nodes
> into the production test procedure.
>
> Kolja

An open resistor would fall in the MTBUR prediction since every unit
shall be stressed in thermal and vibration cycles for infant
mortality.
More resistors in parallel would reduce the system MTBF.
The best would be to have a T like structure (2 resistors and a zener
or TVS) in a device with MTBF as high as single resistors or single
diode. This would improve the overall system but I don't know if it
does exist.
-Augusto

AugustoEinsfeldt wrote:
> Thanks for all responses. Because the time zone I was unable to reply
> earlier.
> The device will do a lot of slow timings (1 second to 10 minutes),
> read 6 serial interface ADC converters (with 2.5MHz SCLK) and talk to
> a CPLD (used as port expander and watchdog) at 10Mbps data rate. It is
> a 3S200 and may have up to 70% of resources used.
>
> I may stick to the pull-down resistor idea because the system MTBF.
> Resistors cause less impact here.
> System has a XPLA3 CPLD and other circuits at 3V3 (that is supplied
> by a TDK's DC-DC converter) and I think the excess of current will
> sink easily. But I will calculate it again. TDK's never answered about
> sink capability of their DC-DC modules and I'd like to avoid using a
> 3V6 zener to do not waste energy in some temperature conditions.
> The signal's rise/fall time are around 50us (worst case). I know it is
> very slow for this device and I will have some extra current in the
> pin's input circuitry but the cycle time of each signal is in the
> range of several minutes. So the impact of slow signal transition may
> not be important for the system. Only 2 to 5 signals of 56 may change
> at same time and since they came from mechanical feedback it is very
> unlikely they will really change precisely together.

If you are chasing high operational MTBF, I would be wary of feeding
slow edges into a device running a lot of other logic.
I have seen very strange effects, caused by input theshold oscillations
on Digital devices without hysteresis. High series R makes this effect
worse.
[I think Xilinx fpga's may have small Hyst, you'll need to check ]

> The design did use schmitt-trigger devices for the inputs in the past
> but the MTBF did fall because other added circuits and I thought I
> could work out the bounce and slow edges with some sample/timing logic
> in the FPGA.
>
> Each of these input signals has a transient suppressor and another
> 100ohm resistor to the input connector. Those are to protect against
> huge ESD strikes and EMC/EMI.
>
> Exercising a bit longer in this subject, in case I can sink externally
> (to the FPGA) the excess of current (56mA) and since each clamp diode
> for this device can handle 100mA (according DS099), which leads a good
> current injection handling, the single input resistor (no pull-down)
> could work. I am in the limit of system MTBF and it is why I still
> thinking to avoid any other component... The main question remains:
> would the FPGA's MTBF be reduced because this current flowing in the
> clamp diodes?
>
> System cost is not a big issue but I'd like to avoid high reliability
> resistors because availability and lead times. While writing this text
> I am having second thoughts about avoiding these resistors... but your
> opinion would help in the FPGA's MTBF.

What about 4-Pack resistors ?. That slashes the component count, so
should improve your MTBF.

Another design approach, would be to hold the IP pins low, most of the
time, and tristate for narrow window, and read the Pin status at the end
of that time.
Result is no significant clamp energy, and faster slews - as you now
effectively sense a CURRENT level, not a voltage level.
[ eg at 1mA and 10pF I get 20ns for 0-2V slew]

-jg

On Jul 3, 7:36 pm, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:
> AugustoEinsfeldt wrote:
> > Thanks for all responses. Because the time zone I was unable to reply
> > earlier.
> > The device will do a lot of slow timings (1 second to 10 minutes),
> > read 6 serial interface ADC converters (with 2.5MHz SCLK) and talk to
> > a CPLD (used as port expander and watchdog) at 10Mbps data rate. It is
> > a 3S200 and may have up to 70% of resources used.
>
> > I may stick to the pull-down resistor idea because the system MTBF.
> > Resistors cause less impact here.
> > System has a XPLA3 CPLD and other circuits at 3V3 (that is supplied
> > by a TDK's DC-DC converter) and I think the excess of current will
> > sink easily. But I will calculate it again. TDK's never answered about
> > sink capability of their DC-DC modules and I'd like to avoid using a
> > 3V6 zener to do not waste energy in some temperature conditions.
> > The signal's rise/fall time are around 50us (worst case). I know it is
> > very slow for this device and I will have some extra current in the
> > pin's input circuitry but the cycle time of each signal is in the
> > range of several minutes. So the impact of slow signal transition may
> > not be important for the system. Only 2 to 5 signals of 56 may change
> > at same time and since they came from mechanical feedback it is very
> > unlikely they will really change precisely together.
>
> If you are chasing high operational MTBF, I would be wary of feeding
> slow edges into a device running a lot of other logic.
> I have seen very strange effects, caused by input theshold oscillations
> on Digital devices without hysteresis. High series R makes this effect
> worse.
> [I think Xilinx fpga's may have small Hyst, you'll need to check ]
>
>
>
> > The design did use schmitt-trigger devices for the inputs in the past
> > but the MTBF did fall because other added circuits and I thought I
> > could work out the bounce and slow edges with some sample/timing logic
> > in the FPGA.
>
> > Each of these input signals has a transient suppressor and another
> > 100ohm resistor to the input connector. Those are to protect against
> > huge ESD strikes and EMC/EMI.
>
> > Exercising a bit longer in this subject, in case I can sink externally
> > (to the FPGA) the excess of current (56mA) and since each clamp diode
> > for this device can handle 100mA (according DS099), which leads a good
> > current injection handling, the single input resistor (no pull-down)
> > could work. I am in the limit of system MTBF and it is why I still
> > thinking to avoid any other component... The main question remains:
> > would the FPGA's MTBF be reduced because this current flowing in the
> > clamp diodes?
>
> > System cost is not a big issue but I'd like to avoid high reliability
> > resistors because availability and lead times. While writing this text
> > I am having second thoughts about avoiding these resistors... but your
> > opinion would help in the FPGA's MTBF.
>
> What about 4-Pack resistors ?. That slashes the component count, so
> should improve your MTBF.
>
> Another design approach, would be to hold the IP pins low, most of the
> time, and tristate for narrow window, and read the Pin status at the end
> of that time.
> Result is no significant clamp energy, and faster slews - as you now
> effectively sense a CURRENT level, not a voltage level.
> [ eg at 1mA and 10pF I get 20ns for 0-2V slew]
>
> -jg

Jim, I had exactly the same thought minutes ago and was going to post
it when I saw your message. This sounds a good idea. Important to know
there can happen strange effects with low slew rate signals, so this
approach seems to solve all issues.
Using inout pin and keeping it as output in zero for most of the time
can effectively reduce the stress. I would do the signal sampling in
the previous input design, anyway, so the solution was already half
way.
Thanks,
-Augusto