FPGA Central

Hi All,

I'm trying to develop a serial link using the Aurora protocol between 2
MGT's on a V2pro FF672 based ML321 board. Currently, I'm trying to use
the "Using High Speed Serial MGTs with the Aurora IP" sample design
offered by the Xilinx University program as a starting
point(http://www.xilinx.com/univ/XUPV2P/Qu...v2p_aurora.zip)
I went through the process described in the quickstart guide and got
the Modelsim simulation to work. But, I'm having some issues using
Chipscope to monitor the link. I compiled the design in ISE, and
configured the FPGA module in Chipscope using the bit file. Once I hit
the arm and trigger button; it keeps giving me a message "Waiting for
core to be armed, slow or stopped clock" I believe I've instantiated
the clock modules in the ucf file correclty (I just used the sample ucf
generated by aurora 2.2 & the sample ucf file provided w/ the design) I
recently used the board to run the XAPP661, so I do know that onboard
clock works properly.

Can you think of any other reasons why Chipscope might fail to acquire
data from the board. (My labmate thinks its possible that the design is
not even uploaded to the FPGA even though its configured in Chipscope
because the FPGA chip doesnt get hot/warm)

Thanks in advance,
Billu