FPGA Central

I simulate the ddr controler generated by MIG(memory interface generator). The result of behavior simulation is correct ,but there's someting wrong after synthesis. The wave is unknown after ddr sdram initialization. I affix the captured picture in this mail. I use synplify 8.2.2 to synthesis the design, and use modelsim 6.2a to simulation it.

Hi,
Are you trying to simulate the synthesized model?. i am
working with ddr controller currently.i think we can help each
other.send me your problem in detail.
regards
subin

orthogonal wrote:
> I simulate the ddr controler generated by MIG(memory interface generator). The result of behavior simulation is correct ,but there's someting wrong after synthesis. The wave is unknown after ddr sdram initialization. I affix the captured picture in this mail. I use synplify 8.2.2 to synthesis the design, and use modelsim 6.2a to simulation it.