FPGA Central

Hi considering me a novice. I have a very basic question. How can i
connect multiple user IPs to a shared memory on FPGA. I am using Xilinx
Virtex 4 FX FPGA and want to have a common memory place on chip where
i can save all the signal comming from out side. This common place will
also be used to share the output signal between the custom IP. I am
planning to use BRAM for this purpose but since BRAM is dual port so i
can have only two of the IP attached to it at any time. Please advice
me since this issue is halting my design process. I also want to attach
the processor to that shared memory so it can also share the signals
with rest of user logic residing on FPGA. I am using on chip processor
PowerPC405.

Thanks

Faraz

[email protected] wrote:

> Hi considering me a novice. I have a very basic question. How can i
> connect multiple user IPs to a shared memory on FPGA.

Step one is to instance the synthesis modules into
a schematic or hdl source file and wire them up.

-- Mike Treseler

On 30 Mar 2006 09:17:14 -0800, [email protected] wrote:

>Hi considering me a novice. I have a very basic question. How can i
>connect multiple user IPs to a shared memory on FPGA. I am using Xilinx
>Virtex 4 FX FPGA and want to have a common memory place on chip where
>i can save all the signal comming from out side. This common place will
>also be used to share the output signal between the custom IP. I am
>planning to use BRAM for this purpose but since BRAM is dual port so i
>can have only two of the IP attached to it at any time. Please advice
>me since this issue is halting my design process. I also want to attach
>the processor to that shared memory so it can also share the signals
>with rest of user logic residing on FPGA. I am using on chip processor
>PowerPC405.
>
>Thanks
>
>Faraz

What you need is a mux. A mux is a piece of hardware which take all
the outputs from all IPs and forwards only one of them to its output
based on a control signal so that you can write that value to the
memory. Of course the control signal should be wide enough so that you
can indicate all the inputs ie if you have 8 input, you need a 3 bit
control signal. You also need to tell each IP block that their output
is consumed and you can accomplish that with decoding the control
signal and using the decoded values to enable each IP block (or use it
as a read signal etc.)

HTH.

Do i need to make any interface controller to connect the address and
data lines from the IP to mux or its direct connection to mux