FPGA Central

hey guys,

Problem 1:
i wrote the following code to write 10 'D' to the flash ram after which i
read from the flash ram location 200000 using the FTU. But i got DDDDD D
instead. Can someone please tell me what went wrong. Is there anyway in
which i can phyically see what was written to my ram other than
transfering it to the flash ram and reading it using FTU?

Code:
#define RC100_CLOCK_DIVIDE 20
#define RC100_BOARD
// Include libraries and headers
#include <stdlib.h>
#include <RC100.h>

void main()
{
RC100FlashEnable();

RC100FlashBlockErase(10);
RC100FlashWriteByte( 0x00200000, (unsigned 8)0x44);//ascii D
RC100FlashWriteByte( 0x00200001, (unsigned 8)0x44);
RC100FlashWriteByte( 0x00200002, (unsigned 8)0x44);
RC100FlashWriteByte( 0x00200003, (unsigned 8)0x44);
RC100FlashWriteByte( 0x00200004, (unsigned 8)0x44);
RC100FlashWriteByte( 0x00200005, (unsigned 8)0x44);
RC100FlashWriteByte( 0x00200006, (unsigned 8)0x44);
RC100FlashWriteByte( 0x00200007, (unsigned 8)0x44);
RC100FlashWriteByte( 0x00200008, (unsigned 8)0x44);
RC100FlashWriteByte( 0x00200009, (unsigned 8)0x44);

RC100FlashSetReadMode();
}


Problem 2:
i'm actually trying to communicate with the USB D+
and D- signal using the expansion slot pins on the RC100. The speed is
about 1.5Megabits/s. So i will need to read from the pins at 3MHz. Is
there anyway in which i can set the #define RC100_CLOCK_DIVIDE to 3MHz or
any sampling function that i can use for setting. if i were to used higher
clock rate the using the #define RC100_CLOCK_DIVIDE , i will get much more
data as a logic 1 or 0 will be read several times rather than 1 time only.


Also, can you also please advise on time/length for each output bit that i
output with the below function.


I'm using the following function:
interface bus_ts_clock_in (unsigned int 1 read )
Dplus(unsigned int 1 writePort=z,
unsigned 1 enable=condition)
with {data = {"AA15"} };

Thanks a lot in advance. Really appreciate it if you guys can give me some
advice. Thanks once again.