FPGA Central

Hi,friends,
I use a lattice ispXPLD 5512mv in my design, but i dont use the
goe(global output enable) pins, how should I deal with it? pull down
it?will it affect my design logic?
In my design, there is a pci interface but I dont design the PAR
logic, both perr and serr, how should I connect them? pull up? pull down
or just leave them away?
Thanks a lot!

Regards

not this one wrote -

>Hi,friends,
> I use a lattice ispXPLD 5512mv in my design, but i dont use the
>goe(global output enable) pins, how should I deal with it? pull down
>it?will it affect my design logic?

The GOE pins do not need to be terminated in your design. If your design is
not specifically using them, the will not be connected to any of the I/O, and
the internal pullup in the I/O pad will prevent floats, etc.....

> In my design, there is a pci interface but I dont design the PAR
>logic, both perr and serr, how should I connect them? pull up? pull down
>or just leave them away?

without more info on the design, I can only provide a clue on this one -
if perr or serr are active high, and you aren't using them, either tie the pin
low, or program the pulldown option for the pin, to keep inactive -

the 5K families all provide induvidual pullup/pulldown/bus hold/ none option
for pin configuration -

you might also give your local Lattice FAE a call, he/she would be happy to
help -
> Thanks a lot!
>
>Regards
>
>
have a good day -
Mike Thomas
Lattice SFAE - Ny/NJ