FPGA Central

In my project, which uses an Altera Cyclone EP1C12, I need to generate a
lot of different frequencies, such as f=10Mhz, 1MHz, 2.5MHz, 250kHz, etc.
I used counters but quartus' design assistant complains that I'm using
gated clocks. Are there better solutions than counters to achieve what I
need? Or better ways to implement frequency divisors?
Thank you in advance,
BQ

"BQ" <[email protected]> schrieb im Newsbeitrag
news:mkfue.16513$[email protected]..

> In my project, which uses an Altera Cyclone EP1C12, I need to generate a
> lot of different frequencies, such as f=10Mhz, 1MHz, 2.5MHz, 250kHz, etc.
> I used counters but quartus' design assistant complains that I'm using
> gated clocks. Are there better solutions than counters to achieve what I
> need? Or better ways to implement frequency divisors?

The counters are right, but don't use the outputs as real clocks. Run
everything at the highest frequency (I guess 10 MHz) and use clock enables
for the slower parts of the logic. Keeps things easy and safe.

Regards
Falk

The problem is when you start using the counter bits as clocks.
If your clock is simply one of the counter's bits, this is not really a
gated clock,
there is no problem in terms of that there is no ambiguity of metastability.

Honestly I really hate this thing in Quartus as many other warnings, which
are far from reality.

Try using the same highest clock and counter bits as "clock enable"s.
If you designing a UART-like application, this is the way to go.

Vladislav

"BQ" <[email protected]> wrote in message
news:mkfue.16513$[email protected]..
> In my project, which uses an Altera Cyclone EP1C12, I need to generate a
> lot of different frequencies, such as f=10Mhz, 1MHz, 2.5MHz, 250kHz, etc.
> I used counters but quartus' design assistant complains that I'm using
> gated clocks. Are there better solutions than counters to achieve what I
> need? Or better ways to implement frequency divisors?
> Thank you in advance,
> BQ

Let's look at the basics:
If you have an incoming clock (say 10 MHz in your case) and you want to
derive any clock from it, these derived clocks will inevitably be
delayed from the original clock, even when you are smart and avoid
ripple counters and clock gating. Also, the distribution of your many
clocks might use local (instead of global) routing.
Whatever you do, you end up with a sloppy clock structure, which
invites hold-time problems when the different clock domains have to
interact. (If they don't, you really have no problem.)

Dumb clock gating can create glitches, mixing non-synchronous clocks
can create metastability problem, but even the most careful clock
selection scheme is dangerous.

Clock Enable avoids all these problems (except the metastability).
That's why we all favor CE (except for its higher power consumption).
Peter Alfke, Xilinx Applications

Let's look at the basics:
If you have an incoming clock (say 10 MHz in your case) and you want to
derive any clock from it, these derived clocks will inevitably be
delayed from the original clock, even when you are smart and avoid
ripple counters and clock gating. Also, the distribution of your many
clocks might use local (instead of global) routing.
Whatever you do, you end up with a sloppy clock structure, which
invites hold-time problems when the different clock domains have to
interact. (If they don't, you really have no problem.)

Dumb clock gating can create glitches, mixing non-synchronous clocks
can create metastability problem, but even the most careful clock
selection scheme is dangerous.

Clock Enable avoids all these problems (except the metastability).
That's why we all favor CE (except for its higher power consumption).
Peter Alfke, Xilinx Applications

In HDL you can do something like this:

module clock_generator(input clk, input resetN, output reg CE_out);
parameter clk_divisor = 1;
reg [3:0] cnt;
always @ (posedge clk or negedge resetN)
begin
if (~resetN)
begin
cnt <= 0; CE_out <= 0;
end
else begin
if (cnt == (clk_divisor - 1))
begin
cnt <= 0; CE_out <= 1;
end
else begin
cnt <= cnt + 1; CE_out <= 0;
end
end
end
endmodule
module top(input clk, input resetN, output reg Q1, output reg Q2);
wire CE1;
wire CE2;
defparam U1.clk_divisor = 10; // generate a CE every 10 clocks
clock_generator U1 (.clk(clk),.resetN(resetN),.CE_out(CE1));
defparam U2.clk_divisor = 5; // generate a CE every 5 clocks
clock_generator U2 (.clk(clk),.resetN(resetN),.CE_out(CE2));
always @ (posedge clk or resetN)
begin
if (~resetN) Q1 <= 0; else if (CE1) Q1 <= ~Q1;
if (~resetN) Q2 <= 0; else if (CE2) Q2 <= ~Q2;
end
endmodule

module tb(); //testbench
reg clk,resetN;
wire Q1,Q2;
initial
begin
resetN <= 0;
clk <= 0;
#10 resetN <= 1;
while (1) #100 clk <= ~clk;
end
top UUT(.clk(clk),.resetN(resetN),.Q1(Q1),.Q2(Q2));
endmodule

Best to always use a single clock whenever possible. If you need to
divide more than 16 you'll have to grow cnt, of course...