FPGA Central

Jidan Al-Eryani, one of my students, has implemented an FPU [1]
which is now available for JOP. The FPU is connected via the
SimpCon [2] bus and can be accessed as an IO device. That's not
the most efficient solution, but ok for the first tests.

Compared to the Verilog FPU at opencores, this one is written
in VHDL, smaller and fully registerd. It can be clocked with
100MHz on a Cyclone C6 (instead of about 6MHz the fully
asynchronous Verilog FPU).

As the FPU is not enough tested the floating point bytecodes
(from JOP) do not access the FPU at the moment.

If you are interested in using the FPU with JOP see
..../test/fpu/Basic.java how to access the FPU. Perhaps you
can help to test it.

The Quartus project the contains the FPU is 'cycfpu'. All
sources are available from CVS [3]. Check them out with:

cvs -d server:[email protected]:/cvsroot/anonymous -z9 co -P jop

change the project in the Makefile to 'cycfpu' (instead of 'cycmin')

and build the project with

make -e P1=test P2=fpu P3=basic

Martin

[1] http://www.opencores.org/projects.cg...pu100/overview
[2] http://www.opencores.org/projects.cg...mpcon/overview
[3] http://www.opencores.org/projects.cgi/web/jop/overview