 |
FPGA CentralWorld's 1st FPGA Portal |
|
|
|
|||||||
| FPGA comp.arch.fpga newsgroup (usenet) |
|
|
|
 |
|
|
LinkBack | Thread Tools | Display Modes |
12-10-2003, 10:37 AM
|
|||
|
|||
Re: Finding Multicyle Paths in a Design
Hi Muthu,
I don't believe you will find a script to do this. However, static property checkers like Averant's Solidify (www.averant.com) can autocheck for multicycle path violations. Regards, Hans. www.ht-lab.com "Muthu" <[email protected]> wrote in message news:28[email protected] om... > Hi, > > Is there any script kind of, which can scan the RTL files and list out > the Available Multicyle paths ? > > It is possible. Isn't it? > > Regards, > Muthu 
|
|
12-16-2003, 12:40 AM
|
|||
|
|||
|
Re: Finding Multicyle Paths in a Design
There is a product (Focus) from Fish Tail Design Autmation that does this.
http://www.fishtail-da.com "Hans" <[email protected]> wrote in message news:BPBBb.85$[email protected].. > Hi Muthu, > > I don't believe you will find a script to do this. However, static property > checkers like Averant's Solidify (www.averant.com) can autocheck for > multicycle path violations. > > Regards, > > Hans. > > www.ht-lab.com > > "Muthu" <[email protected]> wrote in message > news:[email protected] om... > > Hi, > > > > Is there any script kind of, which can scan the RTL files and list out > > the Available Multicyle paths ? > > > > It is possible. Isn't it? > > > > Regards, > > Muthu > >
|
|
| Bookmarks |
| Thread Tools | |
| Display Modes | |
Linear Mode
|
|
Similar Threads
|
||||
| Thread | Thread Starter | Forum | Replies | Last Post |
| Stating Timing Analysis - Timing-Critical Paths & False Paths | Chloe | Verilog | 5 | 05-09-2005 08:13 PM |
| finding all X's with NC | Chris Briggs | Verilog | 6 | 10-04-2003 01:37 AM |
| Max finding | Josh Model | FPGA | 4 | 08-29-2003 02:54 AM |
All times are GMT +1. The time now is 02:37 AM.
