FPGA Central

In the Xilinx Virtex 4 architecture, does anyone know when you
instantiate a FIFO using the FIFO16 blocks does the FIFO use the
RAMB16 block next to it for its memory, or does the FIFO16 has its own
dedicated memory (thus leaving the RAMB16 free for other uses)?

Erik Anderson wrote:
> In the Xilinx Virtex 4 architecture, does anyone know when you
> instantiate a FIFO using the FIFO16 blocks does the FIFO use the
> RAMB16 block next to it for its memory, or does the FIFO16 has its own
> dedicated memory (thus leaving the RAMB16 free for other uses)?

The FIFO16:

http://toolbox.xilinx.com/docsan/xil...sc0092_83.html

uses dedicated logic to turn a BlockRAM into a FIFO, either
synchronous or asyncronous. Using one of these large FIFOs will use a
BlockRAM. Smaller FIFOs can be implemented in distributed logic,
however, leveraging the Shift Register memory mode of the LUTs for the
synchronous FIFO. Many synthesizers will imply shift registers
properly if you design the synchronous FIFO to leverage the silicon
properly. Async FIFOs are a little more difficult in distributed
memory and must use the dual-port mode but can work beautifully for
small FIFOs.

So how large are you going for?