FPGA Central

Hello all,

I have to design a FPGA which is located solely in a small board (DB). The
DB is connected to the main board with a connector whose schematic I have
(all exhanged signals locations). I am requested to deliver a pinout of my
FPGA, can someone tell me which are the constraints of this task? The only
constraint I have in mind is that signals belonging to the same bus must be
placed to pins that are very close (bit 0 next to bit 1 and so on). The
timing of all signals is not critical since the maximum clock frequency of
the signals is 78MHz and the technology used is LVTTL.

Thanks in advance for your help

On Mon, 5 Apr 2004 11:23:36 +0300, "alphaboran"
<[email protected]> wrote:

>Hello all,
>
>I have to design a FPGA which is located solely in a small board (DB). The
>DB is connected to the main board with a connector whose schematic I have
>(all exhanged signals locations). I am requested to deliver a pinout of my
>FPGA, can someone tell me which are the constraints of this task?

>The only
>constraint I have in mind is that signals belonging to the same bus must be
>placed to pins that are very close (bit 0 next to bit 1 and so on).

This is probably the *worst* pinout from the point of view of ground
bounce. Read the guidelines for SSOs in the datasheet. You can have
a maximum number of outputs per VCC/GND pair, or a maximum number of
outputs per I/O bank. (The datasheet will have the maximum numbers
allowable, and this number will differ with the I/O standard used.
LVTTL is one of the worst!)

Also add grounds to regular I/O pins close to your clock inputs. (Use
floorplanner or fpga editor to work out which pins are closest on the
die. This isn't always the same as "close" on the BGA balls.)

Make your clock inputs differential if possible.

IIRC, one of the Xilinx app notes recommended adding grounds to
regular I/O pins around the DCMs. Again, use floorplanner or fpga
editor to work out which pins these are.

Regards,
Allan.