FPGA Central

Hi,

I am trying to access a QuickLogic FPGA via JTAG. I am using a FTDI
DLP2232M-G (and associated FTCJTAG api) to connect to the device.

So far I have been able to read and write data to the device
sucessfully, or at least i think so!

My problem is, that presented with a read / write API functions I have
no idea as to what I *should* be writing to or reading from the FPGA
and to which registers (instruction / test). My goal (at least for
now) is to sample the state of every pin on the device.

My question is this: does anyone know the commands needed to sample
the state of every pin on the FPGA and if so how do I interpret what I
read back?

Please bear in mind that I am a software engineer and know virtually
nothing about FPGA's and very little about JTAG (dispite reading the
IEEE standard and understanding very little).

Thanks in advance for any help.

_TK_

On 2008-06-19, _TK_ <tom_kuhn@btopenworld.com> wrote:
> My problem is, that presented with a read / write API functions I have
> no idea as to what I *should* be writing to or reading from the FPGA
> and to which registers (instruction / test). My goal (at least for
> now) is to sample the state of every pin on the device.

This information is usually provided in BSDL (Boundary Scan Description
Language) files. Try to ask Quicklogic about this. (A quick search at
quicklogic.com didn't turn up anything when I tried it.)

/Andreas

HI all

This may be a bit late too help you but I just came across a new Free JTAG tool for pin-toggling and contiunuity testing. It can be downloaded form
www.jtaglive.com and it will work on Altera and Xilinx cables but not yet Quicklogic I think.

Since it is based on the JTAG/boundary-scan IEEE Std 1149 it works with all FPGAs and other JTAG parts. It will import the BSDL file referred to above an enable you to set up pin toggles without any JTAG knowledge. Might be worth a look.

Cheers

Des