FPGA Central

in an EDK project, is it possible (as with ISE) to verify vhdl syntax
of one file, before a long long make that abort complaining that syntax
of a user_logic.vhdl is missing some ; or ' ...

batch compilation would be a must

rpons...@gmail.com schrieb:

> in an EDK project, is it possible (as with ISE) to verify vhdl syntax
> of one file, before a long long make that abort complaining that syntax
> of a user_logic.vhdl is missing some ; or ' ...
>
> batch compilation would be a must

you can setup and ISE project or batch file for this
there is IMHO no other solution at the moment

Antti

[email protected] wrote:
> in an EDK project, is it possible (as with ISE) to verify vhdl syntax
> of one file, before a long long make that abort complaining that syntax
> of a user_logic.vhdl is missing some ; or ' ...
>
> batch compilation would be a must
>

You can place your user designed logic at the top of the .mhs file. In this case
it is the first block which is synthesized.

Frank