FPGA Central

I just begining my work on dynamic partial reconfiguration of Xilinx
Virtex-4 FPGAs. I have readed those article sur the site of Xilinx
e.g; the guild of configuration , use guid etc. but I havent also any
idea for the begining. I wish someone can give me a real exemple or
some advices for the dynamic partial reconfiguration of Virtex-4.

thanks on advance,

xun

Hi xun,
Check out Xilinx's PlanAhead product. Quote:-
"New Partial Reconfiguration features and capabilities in PlanAhead 8.1
simplify the implementation of this complex but powerful design flow.
Combined with the ISE 8.1i Design Tools, PlanAhead 8.1 delivers the
industry's only front-to-back solution for partial reconfiguration."
www.xilinx.com/planahead
Make sure you report back to let us know how you're getting along!
Good luck (you'll need it!) Syms.

<[email protected]> wrote in message
news:[email protected] oups.com...
>I just begining my work on dynamic partial reconfiguration of Xilinx
> Virtex-4 FPGAs. I have readed those article sur the site of Xilinx
> e.g; the guild of configuration , use guid etc. but I havent also any
> idea for the begining. I wish someone can give me a real exemple or
> some advices for the dynamic partial reconfiguration of Virtex-4.
>
> thanks on advance,
>
> xun
>

Partial REconfiguration on Virtex-4 using ISE8.1 doesnt work.

Good Luck

On 14 Feb 2006 06:58:17 -0800, [email protected] wrote:

>I just begining my work on dynamic partial reconfiguration of Xilinx
>Virtex-4 FPGAs. I have readed those article sur the site of Xilinx
>e.g; the guild of configuration , use guid etc. but I havent also any
>idea for the begining. I wish someone can give me a real exemple or
>some advices for the dynamic partial reconfiguration of Virtex-4.
>
>thanks on advance,
>
>xun

I recommend reading the article below:

http://www.fpgajournal.com/articles_...60207_cray.htm

Apparently RC works...
Peter Alfke

Partial reconfig for V4 requires additional software that is not
included in 8.1i.
PlanAhead is also required. You need to contact your local FAE to gain
access
to this software.

Steve

Symon wrote:
> Hi xun,
> Check out Xilinx's PlanAhead product. Quote:-
> "New Partial Reconfiguration features and capabilities in PlanAhead 8.1
> simplify the implementation of this complex but powerful design flow.
> Combined with the ISE 8.1i Design Tools, PlanAhead 8.1 delivers the
> industry's only front-to-back solution for partial reconfiguration."
> www.xilinx.com/planahead
> Make sure you report back to let us know how you're getting along!
> Good luck (you'll need it!) Syms.
>
> <[email protected]> wrote in message
> news:[email protected] oups.com...
>
>>I just begining my work on dynamic partial reconfiguration of Xilinx
>>Virtex-4 FPGAs. I have readed those article sur the site of Xilinx
>>e.g; the guild of configuration , use guid etc. but I havent also any
>>idea for the begining. I wish someone can give me a real exemple or
>>some advices for the dynamic partial reconfiguration of Virtex-4.
>>
>>thanks on advance,
>>
>>xun
>>
>
>
>

Peter,

there is no evidence of _dynamic_ reconfiguration in this article.

Actually, Smith-Waterman algorithm is not a good candidate for
demonstrating dynamicity, because the query sequence occupies only an
edge of the accelerator array => programming a long register is ok.
Changing algorithm coefficients would benefit from DPR, but actually,
biologists never do so!

Xilinx paper "Gene Matching using JBits" in FPL 2002 was an
implementation of the Needleman-Wunsch algorithm (simpler than S-W); it
also uses a run-time query, and implementation is optimized for given
coefficients, so it's not clearly taking advantage of DPR.
Anyway JBits was demonstrated to work.

Stephane

Peter Alfke wrote:
> I recommend reading the article below:
>
> http://www.fpgajournal.com/articles_...60207_cray.htm
>
> Apparently RC works...
> Peter Alfke
>

Of course it works. Self-Reconfiguration on Virtex2,Spartan2 and
Spartan3 works fine. I said that Partial Reconfiguration on Virtex4
using ISE doesnt work. I dont know if using PlanAhead it works.

We have made many experiments and using Virtex4 during the final
assembly phase it fails due to problem with the disabled DCMs, and
many global logic that appears during this phase. That global logic
goes from TIE elements to CE inputs of the registers inside the
slices. For smal designs we have route it manually and we've got some
simple design of PR on Virtex4, but for larger designs is imposible to
route that logic. Appart for it there are a problem about using
Virtex4 block rams in modular design, I reported it, and it supposed
to be solved in a IP update for ISE8.1. I havent test it yet.

Yesterday, when I downloaded SP2 for ISE8.1 I tested again the designs
and the problem of the global logic and unconnected DCMs havent
disappear.

Regards

Javier

On 14 Feb 2006 14:16:00 -0800, "Peter Alfke" <[email protected]> wrote:

>I recommend reading the article below:
>
>http://www.fpgajournal.com/articles_...60207_cray.htm
>
>Apparently RC works...
>Peter Alfke

The Virtex4 hardware supports partial reconfiguration and includes a lot
of special hooks intended to increase the flexibility of usage of
Partial Reconfig. Unfortunately the tools haven't quite caught up yet.
This should improve with the new Plan Ahead 8.1 and future Software
releases. Some applications like Software Defined Radio and
Reconfigurable Computing are driving this.

If you run into a problem please call the hotline or file a CR. If
Partial Reconfig is important to you - let your local FAE know. That way
in the future the software and tool support for Partial Reconfiguration
will get the priority it deserves.

- Vic

Javier Castillo wrote:
> Of course it works. Self-Reconfiguration on Virtex2,Spartan2 and
> Spartan3 works fine. I said that Partial Reconfiguration on Virtex4
> using ISE doesnt work. I dont know if using PlanAhead it works.
>
> We have made many experiments and using Virtex4 during the final
> assembly phase it fails due to problem with the disabled DCMs, and
> many global logic that appears during this phase. That global logic
> goes from TIE elements to CE inputs of the registers inside the
> slices. For smal designs we have route it manually and we've got some
> simple design of PR on Virtex4, but for larger designs is imposible to
> route that logic. Appart for it there are a problem about using
> Virtex4 block rams in modular design, I reported it, and it supposed
> to be solved in a IP update for ISE8.1. I havent test it yet.
>
> Yesterday, when I downloaded SP2 for ISE8.1 I tested again the designs
> and the problem of the global logic and unconnected DCMs havent
> disappear.
>
> Regards
>
> Javier
>
> On 14 Feb 2006 14:16:00 -0800, "Peter Alfke" <[email protected]> wrote:
>
>
>>I recommend reading the article below:
>>
>>http://www.fpgajournal.com/articles_...60207_cray.htm
>>
>>Apparently RC works...
>>Peter Alfke

Hi Xun,
Planahead 8.1 supports partial reconfiguration in Virtex 4.
Check out this recent article:
http://www.us.design-reuse.com/news/news12519.html

-Love
http://www.ics.uci.edu/~lsinghal

"Love Singhal" <[email protected]> wrote in message
news:[email protected] oups.com...
> Hi Xun,
> Planahead 8.1 supports partial reconfiguration in Virtex 4.
> Check out this recent article:
> http://www.us.design-reuse.com/news/news12519.html
>
> -Love
> http://www.ics.uci.edu/~lsinghal
>

Hi Singhal,

has the partial reconfig evolved since last time the Virtex 2 nightmare?
I did partial reconfig with V2 FPGAs, and it was really buggy and
inflexible.

Vic Vadi wrote:
> The Virtex4 hardware supports partial reconfiguration and includes a lot
> of special hooks intended to increase the flexibility of usage of
> Partial Reconfig. Unfortunately the tools haven't quite caught up yet.
> This should improve with the new Plan Ahead 8.1 and future Software
> releases.
This is exactly what I've been hearing since I started out with partial
reconfiguration, and that was with ISE4.2. "Will be fixed in the next
service pack", "should work in the next release", "This is not supported
yet, but well be later on.", "This is a known issue that is scheduled to
be fixed in a future software release.".
Kind of reminds me of GNU/Hurd, which is always scheduled to be usable
"next year", or "Duke Nukem Forever", which has been scheduled to be
released for the past 9 years.

Now it's 4 major releases and probably a dozen service packs later, and
the bottom line is: It has never worked properly, it still doesn't, and
in the past few years support in the tools hasn't even gotten a little
better, because all the problems seem to be re-introduced with every
major release all over again. And of course, as soon as a new FPGA
family is introduced (Spartan 3, Virtex 4), all the effort seems to be
going (understandably) into implementing partial reconfiguration for
these new devices, not into fixing bugs in the existing support for
older devices.

The high-point of all of this was with the release of ISE7.1, when
partial reconfiguration was completely disabled until SP4.

> Some applications like Software Defined Radio and
> Reconfigurable Computing are driving this.
Nice to hear that now *finally* there seem to be applications for the
mass market that make the whole subject "interesting" to Xilinx.

In past years the whole thing was more or less academic in nature, and I
totally understand that priorities are low when there's only little or
no money behind it. This is all perfectly reasonable and understandable.

But the thing that bugs me is that Xilinx has been using partial
reconfiguration to promote their parts for years, and as soon as you
really dive into the subject you find out that the parts do indeed
support it, but the software does not, or has only very buggy or
rudimentary support.

So when you ask someone from Xilinx you usually get a link to some
marketing press release which states "Yes, partial reconfiguration
works, we're better than all of our competitors!", which is obviously
only part of the truth...

cu,
Sean

Hi,

I think than actually the PR is well-supported in Virtex-II. This family
is the reference device for all PR documents. But it depends of the
complexity of your design.

The question is if new families will be supported, particularly
Virtex-4, because the new architecture appears to be incompatible with
the actual PR methodology. PlanAhead should be the solution. However it
is necessary to evaluate if it works well for all kind of applications,
because simple PR design works perfectly in all devices: Spartan-II,
Virtex, Virtex-II, etc... as Javier Castillo said.

Regards,

Ivan

Frank wrote:
> "Love Singhal" <[email protected]> wrote in message
> news:[email protected] oups.com...
>> Hi Xun,
>> Planahead 8.1 supports partial reconfiguration in Virtex 4.
>> Check out this recent article:
>> http://www.us.design-reuse.com/news/news12519.html
>>
>> -Love
>> http://www.ics.uci.edu/~lsinghal
>>
>
> Hi Singhal,
>
> has the partial reconfig evolved since last time the Virtex 2 nightmare?
> I did partial reconfig with V2 FPGAs, and it was really buggy and
> inflexible.
>
>
>

Hi,

your comments reveal that you are very annoyed about PR. I think it is a
hard work to make use of it, but actually there are a lot of interesting
applications and research works when PR has been applied successfully.

Of course these good results have been obtained at present. When ISE 4.2
was released, the PR was well-supported by the JBits tool. You chose the
wrong tool

Regards,

Ivan


Sean Durkin wrote:
> Vic Vadi wrote:
>> The Virtex4 hardware supports partial reconfiguration and includes a lot
>> of special hooks intended to increase the flexibility of usage of
>> Partial Reconfig. Unfortunately the tools haven't quite caught up yet.
>> This should improve with the new Plan Ahead 8.1 and future Software
>> releases.
> This is exactly what I've been hearing since I started out with partial
> reconfiguration, and that was with ISE4.2. "Will be fixed in the next
> service pack", "should work in the next release", "This is not supported
> yet, but well be later on.", "This is a known issue that is scheduled to
> be fixed in a future software release.".
> Kind of reminds me of GNU/Hurd, which is always scheduled to be usable
> "next year", or "Duke Nukem Forever", which has been scheduled to be
> released for the past 9 years.
>
> Now it's 4 major releases and probably a dozen service packs later, and
> the bottom line is: It has never worked properly, it still doesn't, and
> in the past few years support in the tools hasn't even gotten a little
> better, because all the problems seem to be re-introduced with every
> major release all over again. And of course, as soon as a new FPGA
> family is introduced (Spartan 3, Virtex 4), all the effort seems to be
> going (understandably) into implementing partial reconfiguration for
> these new devices, not into fixing bugs in the existing support for
> older devices.
>
> The high-point of all of this was with the release of ISE7.1, when
> partial reconfiguration was completely disabled until SP4.
>
>> Some applications like Software Defined Radio and
>> Reconfigurable Computing are driving this.
> Nice to hear that now *finally* there seem to be applications for the
> mass market that make the whole subject "interesting" to Xilinx.
>
> In past years the whole thing was more or less academic in nature, and I
> totally understand that priorities are low when there's only little or
> no money behind it. This is all perfectly reasonable and understandable.
>
> But the thing that bugs me is that Xilinx has been using partial
> reconfiguration to promote their parts for years, and as soon as you
> really dive into the subject you find out that the parts do indeed
> support it, but the software does not, or has only very buggy or
> rudimentary support.
>
> So when you ask someone from Xilinx you usually get a link to some
> marketing press release which states "Yes, partial reconfiguration
> works, we're better than all of our competitors!", which is obviously
> only part of the truth...
>
> cu,
> Sean

It's great to see so much interest in partial reconfiguration. I posted on
Feb 14, but mayby wasn't clear. We have developed new tools and a new flow
for partial reconfig. That software works with ISE 8.1i, but is not
included with
ISE 8.1i. You need to contact your local FAE to get the software.

Steve

Sean Durkin wrote:
> Vic Vadi wrote:
>
>>The Virtex4 hardware supports partial reconfiguration and includes a lot
>>of special hooks intended to increase the flexibility of usage of
>>Partial Reconfig. Unfortunately the tools haven't quite caught up yet.
>>This should improve with the new Plan Ahead 8.1 and future Software
>>releases.
>
> This is exactly what I've been hearing since I started out with partial
> reconfiguration, and that was with ISE4.2. "Will be fixed in the next
> service pack", "should work in the next release", "This is not supported
> yet, but well be later on.", "This is a known issue that is scheduled to
> be fixed in a future software release.".
> Kind of reminds me of GNU/Hurd, which is always scheduled to be usable
> "next year", or "Duke Nukem Forever", which has been scheduled to be
> released for the past 9 years.
>
> Now it's 4 major releases and probably a dozen service packs later, and
> the bottom line is: It has never worked properly, it still doesn't, and
> in the past few years support in the tools hasn't even gotten a little
> better, because all the problems seem to be re-introduced with every
> major release all over again. And of course, as soon as a new FPGA
> family is introduced (Spartan 3, Virtex 4), all the effort seems to be
> going (understandably) into implementing partial reconfiguration for
> these new devices, not into fixing bugs in the existing support for
> older devices.
>
> The high-point of all of this was with the release of ISE7.1, when
> partial reconfiguration was completely disabled until SP4.
>
>
>>Some applications like Software Defined Radio and
>>Reconfigurable Computing are driving this.
>
> Nice to hear that now *finally* there seem to be applications for the
> mass market that make the whole subject "interesting" to Xilinx.
>
> In past years the whole thing was more or less academic in nature, and I
> totally understand that priorities are low when there's only little or
> no money behind it. This is all perfectly reasonable and understandable.
>
> But the thing that bugs me is that Xilinx has been using partial
> reconfiguration to promote their parts for years, and as soon as you
> really dive into the subject you find out that the parts do indeed
> support it, but the software does not, or has only very buggy or
> rudimentary support.
>
> So when you ask someone from Xilinx you usually get a link to some
> marketing press release which states "Yes, partial reconfiguration
> works, we're better than all of our competitors!", which is obviously
> only part of the truth...
>
> cu,
> Sean

Hi Frank,
>From what I have read in the documents (I have not implemented the
complete flow yet), the support for partial reconfiguration has indeed
evolved in Virtex 4.
First, the Planahead tool handles modular based flow better than just
the floorplanner in the previous modular based flow.
Second, the Virtex 4 has fixed size frames (16 clbs) based partial
reconfiguration rather than a column based partial reconfiguration.
This basically means that there can be multiple frames in one column of
any Virtex 4 device. Thus, the whole column does not have to be
reconfigured all at once. This could reduce a lot of complexity for
interconnects that connects one side of reconfigurable region to
another side (they do not have to be routed using long wires only, for
example).
I think designs with partial reconfiguration could be implemented
better in Virtex 4 than in Virtex 2, but as I said, I have not yet
implemented the complete flow.

Love Singhal
http://www.ics.uci.edu/~lsinghal

"Steve Lass" <[email protected]> wrote in message
news:[email protected]..
> It's great to see so much interest in partial reconfiguration. I posted
> on
> Feb 14, but mayby wasn't clear. We have developed new tools and a new
> flow
> for partial reconfig. That software works with ISE 8.1i, but is not
> included with
> ISE 8.1i. You need to contact your local FAE to get the software.
>
Hi Steve,
Are any non-academic customers using this flow with reliable success? My
point being, it's probably a great post-graduate project, but should I be
willing to bet my companies R&D money on it? Is there a commitment from
Xilinx to support this design flow into the future? I'd like to see some IP
cores based on this being released by Xilinx. It would show that the Xilinx
IP developers believe in it!
Please don't get me wrong, I'm typing in a friendly tone of voice! I really
hope you guys have it cracked this time. I hope you can understand the
caution expressed by some of the more cynical posters on CAF!!
Many thanks, Syms.

"Symon" <[email protected]> wrote in message
news:44083507$0$15795$[email protected]..
> willing to bet my companies R&D money on it? Is there a commitment from
I meant "company's". Arse.

Hi Symon,

I think that the use of PR is not related with the money of companies.
The real question will be: is there any kind of application where PR is
really necessary? Companies try to reduce the cost of the products, and
the research and development is only necessary when the solution is not
available with the current technology... why they have to use PR in
their designs when they do not need it?

Moreover, you need to understand that some of academic
researches/customers (as you said) are using PR in their projects
because they are financed by companies. They are looking for this kind
of applications... like Xilinx people, I think.

Regards,

Ivan


Symon wrote:
> "Steve Lass" <[email protected]> wrote in message
> news:[email protected]..
>> It's great to see so much interest in partial reconfiguration. I posted
>> on
>> Feb 14, but mayby wasn't clear. We have developed new tools and a new
>> flow
>> for partial reconfig. That software works with ISE 8.1i, but is not
>> included with
>> ISE 8.1i. You need to contact your local FAE to get the software.
>>
> Hi Steve,
> Are any non-academic customers using this flow with reliable success? My
> point being, it's probably a great post-graduate project, but should I be
> willing to bet my companies R&D money on it? Is there a commitment from
> Xilinx to support this design flow into the future? I'd like to see some IP
> cores based on this being released by Xilinx. It would show that the Xilinx
> IP developers believe in it!
> Please don't get me wrong, I'm typing in a friendly tone of voice! I really
> hope you guys have it cracked this time. I hope you can understand the
> caution expressed by some of the more cynical posters on CAF!!
> Many thanks, Syms.
>
>

Symon,

I can't give you the names of the companies, as we have non-disclosure
policies. I can direct you to our web pages that have customer
testimonials and press releases.

I will say that for development of software defined radio (SDR),
reconfigurability is the only practical solution (OK, IMHO). As such,
we have been highly motivated to make it (the flow) work (better) by the
demand from companies supplying advanced communications from around the
entire globe who also believe as we do.

Is it perfect yet? No.

Is it something people are investing megabucks in?

You bet. SDR for JTRS is a $5 billion program for the next 7 years
(just one program). Like any military program you can expect that to
overrun by ten or twenty times that.

Is all that $$ FPGA chips? No, of course not. There are batteries,
antennnas, plastic cases, etc.

Is it enough $$ to have FPGA and DSP companies sit up and take notice? Yup.

Austin

Symon wrote:

> "Steve Lass" <[email protected]> wrote in message
> news:[email protected]..
>
>>It's great to see so much interest in partial reconfiguration. I posted
>>on
>>Feb 14, but mayby wasn't clear. We have developed new tools and a new
>>flow
>>for partial reconfig. That software works with ISE 8.1i, but is not
>>included with
>>ISE 8.1i. You need to contact your local FAE to get the software.
>>
>
> Hi Steve,
> Are any non-academic customers using this flow with reliable success? My
> point being, it's probably a great post-graduate project, but should I be
> willing to bet my companies R&D money on it? Is there a commitment from
> Xilinx to support this design flow into the future? I'd like to see some IP
> cores based on this being released by Xilinx. It would show that the Xilinx
> IP developers believe in it!
> Please don't get me wrong, I'm typing in a friendly tone of voice! I really
> hope you guys have it cracked this time. I hope you can understand the
> caution expressed by some of the more cynical posters on CAF!!
> Many thanks, Syms.
>
>

Ivan,

Software defined radio is one application. And even here, there are
people who say that DSP can also do the job for less cost/power.

Spacecraft traveling to other planets is another (although you could
argue that they just need to be reprogrammed, and not dynamically).

Also possibly orbiting communications satellites.

So far, there is more solution than problem.

There are examples where a vendor did something very clever, and saved
money and had a competitive advantage using dynamic reconfiguration, but
nothing that has taken the world by storm.

Austin

Ivan wrote:

> Hi Symon,
>
> I think that the use of PR is not related with the money of companies.
> The real question will be: is there any kind of application where PR is
> really necessary? Companies try to reduce the cost of the products, and
> the research and development is only necessary when the solution is not
> available with the current technology... why they have to use PR in
> their designs when they do not need it?
>
> Moreover, you need to understand that some of academic
> researches/customers (as you said) are using PR in their projects
> because they are financed by companies. They are looking for this kind
> of applications... like Xilinx people, I think.
>
> Regards,
>
> Ivan
>
>
> Symon wrote:
>
>> "Steve Lass" <[email protected]> wrote in message
>> news:[email protected]..
>>
>>> It's great to see so much interest in partial reconfiguration. I
>>> posted on
>>> Feb 14, but mayby wasn't clear. We have developed new tools and a
>>> new flow
>>> for partial reconfig. That software works with ISE 8.1i, but is not
>>> included with
>>> ISE 8.1i. You need to contact your local FAE to get the software.
>>>
>> Hi Steve,
>> Are any non-academic customers using this flow with reliable success?
>> My point being, it's probably a great post-graduate project, but
>> should I be willing to bet my companies R&D money on it? Is there a
>> commitment from Xilinx to support this design flow into the future?
>> I'd like to see some IP cores based on this being released by Xilinx.
>> It would show that the Xilinx IP developers believe in it!
>> Please don't get me wrong, I'm typing in a friendly tone of voice! I
>> really hope you guys have it cracked this time. I hope you can
>> understand the caution expressed by some of the more cynical posters
>> on CAF!!
>> Many thanks, Syms.
>>
>>

Hi Ivan,
Thanks for your reply, I've included some comments for your perusal!
"Ivan" <[email protected]> wrote in message
news:%rZNf.706502$[email protected] ..
> Hi Symon,
>
> I think that the use of PR is not related with the money of companies. The
> real question will be: is there any kind of application where PR is really
> necessary? Companies try to reduce the cost of the products, and the
> research and development is only necessary when the solution is not
> available with the current technology... why they have to use PR in their
> designs when they do not need it?
>
When it gives them a competitive advantage in their market. IMO the use of
PR in a commercial environment is absolutely related to money by definition.
That's what companies (try to) do, invest money to make money. My point is
that I've not heard of a single successful commercial project using PR. (NB.
That doesn't mean there haven't been any, just I've not heard of one.) I
think this is because it's too expensive in terms of R&D investment and the
tool chain has a support lifetime of about a year!
>
> Moreover, you need to understand that some of academic
> researches/customers (as you said) are using PR in their projects because
> they are financed by companies. They are looking for this kind of
> applications... like Xilinx people, I think.
>
I already understand this, I think. Companies use students to experiment
with PR because real engineers are too expensive to waste on something
that's not ready for prime-time. (Tongue-in-cheek alert for that last
sentence!) It's also a good educational project I believe. You learn that
not everything's possible! ;-)
As I said, it'd be great if Xilinx's new tool flow works, but it's a big
gamble given PRs track record.
Thanks again, Syms.

"Austin Lesea" <[email protected]> wrote in message
news:du9o62$[email protected]..
> Symon,
>
> I can't give you the names of the companies, as we have non-disclosure
> policies. I can direct you to our web pages that have customer
> testimonials and press releases.
>
> I will say that for development of software defined radio (SDR),
> reconfigurability is the only practical solution (OK, IMHO). As such, we
> have been highly motivated to make it (the flow) work (better) by the
> demand from companies supplying advanced communications from around the
> entire globe who also believe as we do.
>
> Is it perfect yet? No.
>
> Is it something people are investing megabucks in?
>
> You bet. SDR for JTRS is a $5 billion program for the next 7 years (just
> one program). Like any military program you can expect that to overrun by
> ten or twenty times that.
>
> Is all that $$ FPGA chips? No, of course not. There are batteries,
> antennnas, plastic cases, etc.
>
> Is it enough $$ to have FPGA and DSP companies sit up and take notice?
> Yup.
>
> Austin
>
Hi Austin,
Thanks for your post, can you point me to those press releases? I agree with
you SDR could be a good application for partial reconfiguration. As for the
miltary project, are you suggesting the project will overrun by 10-20 times
the cost or 10-20 times the schedule? :-) Both? I'm not sure my employment
could stand a fraction of either of those!
When I first saw the V4 architecture, it did strike me as more suited to PR
than previous devices, if Xilinx get a stable tool flow, I bet you'll get a
competitive advantage from it.
Best regards, Syms.

Hi Austin,

I agree with you. I know about the possibilities of partial
reconfiguration because I have been using (and continuous on it) PR
during the 5 years that I need to finish my PhD. Thesis: JBits, PARBIT,
Modular design (Module-based). I have had to suffer the consequences of
use this technology (like Symon, I think). But finally I finished my
final application: A Hardware-Accelerated SSH on a Self-reconfigurable
MicroBlaze-uCLinux system (using a Spartan-3 device and ISE 6.3). It was
a very big challenge, but it finally works fine in a commercial
Spartan-3 board. Next step... Virtex-4

About your answer, I am very happy to know that there are some
interesting areas that require PR. They are the support that PR needs

Regards,

Ivan


Austin Lesea wrote:
> Ivan,
>
> Software defined radio is one application. And even here, there are
> people who say that DSP can also do the job for less cost/power.
>
> Spacecraft traveling to other planets is another (although you could
> argue that they just need to be reprogrammed, and not dynamically).
>
> Also possibly orbiting communications satellites.
>
> So far, there is more solution than problem.
>
> There are examples where a vendor did something very clever, and saved
> money and had a competitive advantage using dynamic reconfiguration, but
> nothing that has taken the world by storm.
>
> Austin
>
> Ivan wrote:
>
>> Hi Symon,
>>
>> I think that the use of PR is not related with the money of companies.
>> The real question will be: is there any kind of application where PR
>> is really necessary? Companies try to reduce the cost of the products,
>> and the research and development is only necessary when the solution
>> is not available with the current technology... why they have to use
>> PR in their designs when they do not need it?
>>
>> Moreover, you need to understand that some of academic
>> researches/customers (as you said) are using PR in their projects
>> because they are financed by companies. They are looking for this kind
>> of applications... like Xilinx people, I think.
>>
>> Regards,
>>
>> Ivan
>>
>>
>> Symon wrote:
>>
>>> "Steve Lass" <[email protected]> wrote in message
>>> news:[email protected]..
>>>
>>>> It's great to see so much interest in partial reconfiguration. I
>>>> posted on
>>>> Feb 14, but mayby wasn't clear. We have developed new tools and a
>>>> new flow
>>>> for partial reconfig. That software works with ISE 8.1i, but is not
>>>> included with
>>>> ISE 8.1i. You need to contact your local FAE to get the software.
>>>>
>>> Hi Steve,
>>> Are any non-academic customers using this flow with reliable success?
>>> My point being, it's probably a great post-graduate project, but
>>> should I be willing to bet my companies R&D money on it? Is there a
>>> commitment from Xilinx to support this design flow into the future?
>>> I'd like to see some IP cores based on this being released by Xilinx.
>>> It would show that the Xilinx IP developers believe in it!
>>> Please don't get me wrong, I'm typing in a friendly tone of voice! I
>>> really hope you guys have it cracked this time. I hope you can
>>> understand the caution expressed by some of the more cynical posters
>>> on CAF!!
>>> Many thanks, Syms.
>>>
>>>

Symon wrote:
> Hi Ivan,

Hi Symon,

> When it gives them a competitive advantage in their market. IMO the use of
> PR in a commercial environment is absolutely related to money by definition.
> That's what companies (try to) do, invest money to make money. My point is
> that I've not heard of a single successful commercial project using PR. (NB.
> That doesn't mean there haven't been any, just I've not heard of one.) I
> think this is because it's too expensive in terms of R&D investment and the
> tool chain has a support lifetime of about a year!

I do not understand the commercial advantage, if you do not need it to
make your product. Another thing will be the marketing advantage... "we
can do these things" or "we do it more sophisticated". Then I understand
it.

Austin talked about some applications that needs partial
reconfiguration. It possible that SDR requires PR to improve the
flexibility and adaptability of the system. That is the answer that I am
looking for

> I already understand this, I think. Companies use students to experiment
> with PR because real engineers are too expensive to waste on something
> that's not ready for prime-time. (Tongue-in-cheek alert for that last
> sentence!) It's also a good educational project I believe. You learn that
> not everything's possible! ;-)

In my case, when I started my PhD. Thesis I thought that PR was
"impossible mission", but now I believe that PR is possible. I need to
look for another challenge

> As I said, it'd be great if Xilinx's new tool flow works, but it's a big
> gamble given PRs track record.
> Thanks again, Syms.

And I thank you as well.

Regards,

Ivan

Ivan wrote:
> Hi,
>
> your comments reveal that you are very annoyed about PR.
Yes... I did my diploma thesis on it, i.e. on dynamic partial
reconfiguration using the ICAP in Virtex-II Pro devices. The idea was to
use the embedded PowerPC or a Microblaze to reconfigure other parts of
the FPGA doing e.g. image processing. The next step would've been
reconfiguring components of the SoC On-the-Fly. Like you load/unload
Linux kernel modules, you were supposed to be able to load/unload
peripherals for the processor.

The end result was more or less: Yes, it's possible, but there are so
many restrictions and so many problems with the tools that there really
isn't a single application that is worth the immense extra effort you
have to put in simply to make it work somehow. Instead, just get a
bigger FPGA, cram it all in and be done with it.

I literally spent WEEKS doing nothing else than running the same design
over and over and over again, trying all the different command line
switches for all the tools, trying ISE-versions from 4.2 to 6.3 with all
corrresponding EDK-releases and the service packs for each, just to find
one single combination of tools and service packs that wouldn't
constantly quit on me with another dubious "INTERNAL_ERROR" or
"FATAL_ERROR" somewhere along the way.
And every time my boss was as kind as to open a web case for me (as you
don't get support when you're a student, understandably), the answer was
the same: "Will be fixed in the next service pack, currently there is no
work-around", "Is a known bug that will be fixed in the next release"
and so on.

Yeah, they DID fix it in the next release (ISE7.1), by disabling partial
reconfiguration completely. No more "INTERNAL_ERRORS"!

> I think it is a
> hard work to make use of it, but actually there are a lot of interesting
> applications and research works when PR has been applied successfully.
Of course it's INTERESTING... I could think of dozens of things that
would be nice to play around with. But once you're not a student
anymore, you simply don't have the time to play around, unless maybe
you're in research or an academic environment.

But there's no way I'd even think about doing PR in a PRODUCT, unless
it's for small things like changing RocketIO parameters and the like. In
Virtex4 I think you can do PR to change DCM parameters on-the-fly,
that's another thing that seams feasible. But not exchanging whole
modules of logic.

> Of course these good results have been obtained at present. When ISE 4.2
> was released, the PR was well-supported by the JBits tool. You chose the
> wrong tool
Well, JBits didn't handle Virtex-II Pro then. Don't know if it does
now... JBits seemed pretty much dead the last time I checked.

And when I did my thesis, the Virtex-II Pro-bitstream format was still
undisclosed. That would've helped, too...

But, too late now...

Nice to hear that now finally there seem to be tools that really can
handle it, even though they're not shipped with ISE and you even have to
buy some extra, like PlanAhead.

Don't have the time to play around with it, but I'd be glad to hear some
experiences if someone really gets it working reliably.

cu,
Sean