FPGA Central

Hi All,

We are developing a custom borad with Spartan 3A DSP 1800 (FG676) and
dual x16 DDR2 SDRAMs. Address lines shoud be separated for dual memory
controller.
Does anybody know how to create UCF constraints for dual memory
controller in MIG 2.3? Dual memory controllers are only supported for
Virtex 4&5.

Cheers,

Ales

On Jan 25, 11:51*pm, ales.gor...@gmail.com wrote:
> Hi All,
>
> We are developing a custom borad with Spartan 3A DSP 1800 (FG676) and
> dual x16 DDR2 SDRAMs. Address lines shoud be separated for dual memory
> controller.
> Does anybody know how to create UCF constraints for dual memory
> controller in MIG 2.3? Dual memory controllers are only supported for
> Virtex 4&5.
>
> Cheers,
>
> Ales

I guess Xilinx did not see why should anyone want to connect dual bank
DDR2 memories to S3

Maybe the 11.1 do provide support for S3 too, but need wait til may

Antti

On Jan 26, 2:36 pm, Antti <Antti.Luk...@googlemail.com> wrote:
> On Jan 25, 11:51 pm, ales.gor...@gmail.com wrote:
>
> > Hi All,
>
> > We are developing a custom borad with Spartan 3A DSP 1800 (FG676) and
> > dual x16 DDR2 SDRAMs. Address lines shoud be separated for dual memory
> > controller.
> > Does anybody know how to create UCF constraints for dual memory
> > controller in MIG 2.3? Dual memory controllers are only supported for
> > Virtex 4&5.
>
> > Cheers,
>
> > Ales
>
> I guess Xilinx did not see why should anyone want to connect dual bank
> DDR2 memories to S3
>
> Maybe the 11.1 do provide support for S3 too, but need wait til may
>
> Antti

May??? I cannot wait untill May.

ales

On 25 Jan, 21:51, ales.gor...@gmail.com wrote:
> Hi All,
>
> We are developing a custom borad with Spartan 3A DSP 1800 (FG676) and
> dual x16 DDR2 SDRAMs. Address lines shoud be separated for dual memory
> controller.
> Does anybody know how to create UCF constraints for dual memory
> controller in MIG 2.3? Dual memory controllers are only supported for
> Virtex 4&5.
>
> Cheers,
>
> Ales

I've had to do the exact same thing, I did it by generating 2 seperate
MIG cores, and for the second one I use the ucf from the first to
prohibit the pin placements. The generation of the second MIG core
was purely to get a second ucf file. It then involved a bit of manual
playing around with the VHDL to instantiate the second controller, and
then changing the signal names in the second ucf file to those for the
second controller. It was a little while ago that I did this, but I
think that was what I did.

Neill

On Jan 26, 10:28*am, nei...@pipstechnology.co.uk wrote:
> On 25 Jan, 21:51, ales.gor...@gmail.com wrote:
>
> > Hi All,
>
> > We are developing a custom borad with Spartan 3A DSP 1800 (FG676) and
> > dual x16 DDR2 SDRAMs. Address lines shoud be separated for dual memory
> > controller.
> > Does anybody know how to create UCF constraints for dual memory
> > controller in MIG 2.3? Dual memory controllers are only supported for
> > Virtex 4&5.
>
> > Cheers,
>
> > Ales
>
> I've had to do the exact same thing, I did it by generating 2 seperate
> MIG cores, and for the second one I use the ucf from the first to
> prohibit the pin placements. *The generation of the second MIG core
> was purely to get a second ucf file. *It then involved a bit of manual
> playing around with the VHDL to instantiate the second controller, and
> then changing the signal names in the second ucf file to those for the
> second controller. *It was a little while ago that I did this, but I
> think that was what I did.
>
> Neill

Also you want to generate your own clocks, turn off the internal
DCM option when you generate the MIG cores and then you can run
both cores from the same DCM's.

On Jan 26, 4:28 pm, nei...@pipstechnology.co.uk wrote:
> On 25 Jan, 21:51, ales.gor...@gmail.com wrote:
>
> > Hi All,
>
> > We are developing a custom borad with Spartan 3A DSP 1800 (FG676) and
> > dual x16 DDR2 SDRAMs. Address lines shoud be separated for dual memory
> > controller.
> > Does anybody know how to create UCF constraints for dual memory
> > controller in MIG 2.3? Dual memory controllers are only supported for
> > Virtex 4&5.
>
> > Cheers,
>
> > Ales
>
> I've had to do the exact same thing, I did it by generating 2 seperate
> MIG cores, and for the second one I use the ucf from the first to
> prohibit the pin placements. The generation of the second MIG core
> was purely to get a second ucf file. It then involved a bit of manual
> playing around with the VHDL to instantiate the second controller, and
> then changing the signal names in the second ucf file to those for the
> second controller. It was a little while ago that I did this, but I
> think that was what I did.
>
> Neill

Thanks Neill,

That's the info I need. It thought that is my only option if I do not
get any additional info from Xilinx.

Ales

On Jan 26, 4:28 pm, nei...@pipstechnology.co.uk wrote:
> On 25 Jan, 21:51, ales.gor...@gmail.com wrote:
>
> > Hi All,
>
> > We are developing a custom borad with Spartan 3A DSP 1800 (FG676) and
> > dual x16 DDR2 SDRAMs. Address lines shoud be separated for dual memory
> > controller.
> > Does anybody know how to create UCF constraints for dual memory
> > controller in MIG 2.3? Dual memory controllers are only supported for
> > Virtex 4&5.
>
> > Cheers,
>
> > Ales
>
> I've had to do the exact same thing, I did it by generating 2 seperate
> MIG cores, and for the second one I use the ucf from the first to
> prohibit the pin placements. The generation of the second MIG core
> was purely to get a second ucf file. It then involved a bit of manual
> playing around with the VHDL to instantiate the second controller, and
> then changing the signal names in the second ucf file to those for the
> second controller. It was a little while ago that I did this, but I
> think that was what I did.
>
> Neill

Just one more thing: did the internal logic placement constraints
overalp in your case? This can add some more manual editing to be
done.

Cheers,

Ales

On Jan 26, 11:54 pm, Gabor <ga...@alacron.com> wrote:
> On Jan 26, 10:28 am, nei...@pipstechnology.co.uk wrote:
>
>
>
> > On 25 Jan, 21:51, ales.gor...@gmail.com wrote:
>
> > > Hi All,
>
> > > We are developing a custom borad with Spartan 3A DSP 1800 (FG676) and
> > > dual x16 DDR2 SDRAMs. Address lines shoud be separated for dual memory
> > > controller.
> > > Does anybody know how to create UCF constraints for dual memory
> > > controller in MIG 2.3? Dual memory controllers are only supported for
> > > Virtex 4&5.
>
> > > Cheers,
>
> > > Ales
>
> > I've had to do the exact same thing, I did it by generating 2 seperate
> > MIG cores, and for the second one I use the ucf from the first to
> > prohibit the pin placements. The generation of the second MIG core
> > was purely to get a second ucf file. It then involved a bit of manual
> > playing around with the VHDL to instantiate the second controller, and
> > then changing the signal names in the second ucf file to those for the
> > second controller. It was a little while ago that I did this, but I
> > think that was what I did.
>
> > Neill
>
> Also you want to generate your own clocks, turn off the internal
> DCM option when you generate the MIG cores and then you can run
> both cores from the same DCM's.

Of course. I will use external 125MHz oscillator and let EDK to handle
clocks.

Ales

On 27 Jan, 09:55, ales.gor...@gmail.com wrote:
> On Jan 26, 4:28 pm, nei...@pipstechnology.co.uk wrote:
>
>
>
> > On 25 Jan, 21:51, ales.gor...@gmail.com wrote:
>
> > > Hi All,
>
> > > We are developing a custom borad with Spartan 3A DSP 1800 (FG676) and
> > > dual x16 DDR2 SDRAMs. Address lines shoud be separated for dual memory
> > > controller.
> > > Does anybody know how to create UCF constraints for dual memory
> > > controller in MIG 2.3? Dual memory controllers are only supported for
> > > Virtex 4&5.
>
> > > Cheers,
>
> > > Ales
>
> > I've had to do the exact same thing, I did it by generating 2 seperate
> > MIG cores, and for the second one I use the ucf from the first to
> > prohibit the pin placements. *The generation of the second MIG core
> > was purely to get a second ucf file. *It then involved a bit of manual
> > playing around with the VHDL to instantiate the second controller, and
> > then changing the signal names in the second ucf file to those for the
> > second controller. *It was a little while ago that I did this, but I
> > think that was what I did.
>
> > Neill
>
> Just one more thing: did the internal logic placement constraints
> overalp in your case? This can add some more manual editing to be
> done.
>
> Cheers,
>
> Ales

Glad to help. I don't remember there being any overlapping placement
constraints, I know I had to play around with the ucf a bit more later
when I decided to move some of the pins around to make the board
layout a bit easier.

It would be nice if Xilinx would allow MIG to generate dual
controllers for Spartan devices, maybe they'll do it for the Spartan
6, which is due later this year apparently.

Neill.

On Jan 27, 2:55*pm, nei...@pipstechnology.co.uk wrote:
> On 27 Jan, 09:55, ales.gor...@gmail.com wrote:
>
>
>
> > On Jan 26, 4:28 pm, nei...@pipstechnology.co.uk wrote:
>
> > > On 25 Jan, 21:51, ales.gor...@gmail.com wrote:
>
> > > > Hi All,
>
> > > > We are developing a custom borad with Spartan 3A DSP 1800 (FG676) and
> > > > dual x16 DDR2 SDRAMs. Address lines shoud be separated for dual memory
> > > > controller.
> > > > Does anybody know how to create UCF constraints for dual memory
> > > > controller in MIG 2.3? Dual memory controllers are only supported for
> > > > Virtex 4&5.
>
> > > > Cheers,
>
> > > > Ales
>
> > > I've had to do the exact same thing, I did it by generating 2 seperate
> > > MIG cores, and for the second one I use the ucf from the first to
> > > prohibit the pin placements. *The generation of the second MIG core
> > > was purely to get a second ucf file. *It then involved a bit of manual
> > > playing around with the VHDL to instantiate the second controller, and
> > > then changing the signal names in the second ucf file to those for the
> > > second controller. *It was a little while ago that I did this, but I
> > > think that was what I did.
>
> > > Neill
>
> > Just one more thing: did the internal logic placement constraints
> > overalp in your case? This can add some more manual editing to be
> > done.
>
> > Cheers,
>
> > Ales
>
> Glad to help. *I don't remember there being any overlapping placement
> constraints, I know I had to play around with the ucf a bit more later
> when I decided to move some of the pins around to make the board
> layout a bit easier.
>
> It would be nice if Xilinx would allow MIG to generate dual
> controllers for Spartan devices, maybe they'll do it for the Spartan
> 6, which is due later this year apparently.
>
> Neill.

you are well informed
yes its planned in the time frame you mentioned asfaik (s6)
no idea if the mig will allow dual banking for spartan ever tough

Antti

On Jan 25, 11:51*pm, ales.gor...@gmail.com wrote:
> Hi All,
>
> We are developing a custom borad with Spartan 3A DSP 1800 (FG676) and
> dual x16 DDR2 SDRAMs. Address lines shoud be separated for dual memory
> controller.
> Does anybody know how to create UCF constraints for dual memory
> controller in MIG 2.3? Dual memory controllers are only supported for
> Virtex 4&5.
>
> Cheers,
>
> Ales

as the S-6 feature list shows, the first spartan where xilinx will
support dual bank memory controllers is Spartan-6

sure it would be in theory doable for S-3A too, but then Xilinx would
say on any support request:
not supported, please use S-6

what makes me more uneasy about the dual DDR2 in S3A is following line
from the S3ASK starterkit UCF file

==========
# DIRT string to guaranty timing for the feedback path
NET "DDR2_CLK_FB_IBUFG"
ROUTE="{3;1;3s700afg484;99142c6b!-1;-70632;33392;S!0;-159;0!1;-1688;"
"-10424!2;17836;-1100!3;-7468;-19156!4;1624;736!5;559;0;L!}";

==========

Xilinx can make the DDR2 memory to work, but it use

DIRT strings to make it pass timing.
this may become trickier with the dual banks, and well just the PCB
and
timing constraints are gonna be very sensitive for the dual DDR2 to
really
work reliable.

sure with little bit of luck all works as designed first try
but there is no guarantee... and definetly no support from Xilinx in
this regard

Antti