FPGA Central

I have problems with a Microblaze Based Multiprocessor SoC. I have two
Microblaze Cores joined by FSL links. This design works and these
cores can communicate with each other. But now, I am trying to make
these two Microblaze Cores run from an external memory. The linker
script associated with my software applications presents three
possible memories; BRAM (that is, internal ram), DDR_MEM_0 and
DDR_MEM_1. SO, is it possible to load each software application in
each part of the external memory (that is, microblaze_0_app.elf in
DDR_MEM_0, and microblaze_1_app.elf in DDR_MEM_1)?


my best regards

Pablo

On May 25, 8:28*am, pant...@gmail.com wrote:
> I have problems with a Microblaze Based Multiprocessor SoC. I have two
> Microblaze Cores joined by FSL links. This design works and these
> cores can communicate with each other. But now, I am trying to make
> these two Microblaze Cores run from an external memory. The linker
> script associated with my software applications presents three
> possible memories; BRAM (that is, internal ram), DDR_MEM_0 and
> DDR_MEM_1. SO, is it possible to load each software application in
> each part of the external memory (that is, microblaze_0_app.elf in
> DDR_MEM_0, and microblaze_1_app.elf in DDR_MEM_1)?
>
> my best regards
>
> Pablo

I use the MPMC to map memory ports to DDR2 external memory. This
mechanism has been successfully tested with up to 7 microblazes.

/Per

>
> I use the MPMC to map memory ports to DDR2 external memory. This
> mechanism has been successfully tested with up to 7 microblazes.
>
> /Per

Firstly, thanks a lot.

Secondly, I would be grateful if you could tell me if you used XUP
Board and the version of Xilinx Platform Studio. Do you know anything
else of this type of design?

again, my best regards

On May 25, 1:08*pm, Pablo <pbantu...@gmail.com> wrote:
> > I use the MPMC to map memory ports to DDR2 external memory. This
> > mechanism has been successfully tested with up to 7 microblazes.
>
> > /Per
>
> Firstly, thanks a lot.
>
> Secondly, I would be grateful if you could tell me if you used XUP
> Board and the version of Xilinx Platform Studio. Do you know anything
> else of this type of design?
>
> again, my best regards

I've built multi-processors with both mb and ppc using the Xilinx
ML401, ML403, ML505, ML506 demo boards. This works fine under multiple
development environments (virtual pcs with ISE/EDK v9.2 and v10.1).

IMHO the Xilinx docs/tutorials for multi-processors are so thin that
they are not particularly useful. We have a fairly detailed appnote
showing how to design/build/test MPSoC using our high-level tools for
registered users at www.codetronix.com. Go to
Downloads>AppNotes>MPSoC. This shows how to start from a single-
processor BSP-wizard-generated xps system, replicate necessary hw
structures, and download elf files -- it may provide some clues for
you.

/Per

/Per

On 26 mayo, 05:57, lj...@codetronix.com wrote:
> On May 25, 1:08 pm, Pablo <pbantu...@gmail.com> wrote:
>
> > > I use the MPMC to map memory ports to DDR2 external memory. This
> > > mechanism has been successfully tested with up to 7 microblazes.
>
> > > /Per
>
> > Firstly, thanks a lot.
>
> > Secondly, I would be grateful if you could tell me if you used XUP
> > Board and the version of Xilinx Platform Studio. Do you know anything
> > else of this type of design?
>
> > again, my best regards
>
> I've built multi-processors with both mb and ppc using the Xilinx
> ML401, ML403, ML505, ML506 demo boards. This works fine under multiple
> development environments (virtual pcs with ISE/EDK v9.2 and v10.1).
>
> IMHO the Xilinx docs/tutorials for multi-processors are so thin that
> they are not particularly useful. We have a fairly detailed appnote
> showing how to design/build/test MPSoC using our high-level tools for
> registered users atwww.codetronix.com. Go to
> Downloads>AppNotes>MPSoC. This shows how to start from a single-
> processor BSP-wizard-generated xps system, replicate necessary hw
> structures, and download elf files -- it may provide some clues for
> you.
>
> /Per
>
> /Per

thanks again.

I am going to try it just now.


my best regards

On 2009-05-26, [email protected] <[email protected]> wrote:
> I've built multi-processors with both mb and ppc using the Xilinx
> ML401, ML403, ML505, ML506 demo boards. This works fine under multiple
> development environments (virtual pcs with ISE/EDK v9.2 and v10.1).


I've seen quite a few papers about multiprocessor microblaze systems
or multiprocessor nios systems. I'm somewhat curious though, is anyone
using this kind of solution in a commercial setting?

I can understand it for educational purposes, but for commercial
purposes, wouldn't it be better to just buy an embedded multicore
processor of some sort?

/Andreas

> I've seen quite a few papers about multiprocessor microblaze systems
> or multiprocessor nios systems. I'm somewhat curious though, is anyone
> using this kind of solution in a commercial setting?
>

I know of military companies that use this kind of multicore
processors. They usually put embedded solutions and usually need
parallel computation.

> I can understand it for educational purposes, but for commercial
> purposes, wouldn't it be better to just buy an embedded multicore
> processor of some sort?

Of course, but this kind of devices have been designed to find the
ideal solution. Once you have found it, you could but a concret (and
EXPENSIVE) multiprocessor.

This is my poor opinion.

my best regard Andreas.

>On May 25, 1:08=A0pm, Pablo <pbantu...@gmail.com> wrote:
>> > I use the MPMC to map memory ports to DDR2 external memory. This
>> > mechanism has been successfully tested with up to 7 microblazes.
>>
>> > /Per
>>
>> Firstly, thanks a lot.
>>
>> Secondly, I would be grateful if you could tell me if you used XUP
>> Board and the version of Xilinx Platform Studio. Do you know anything
>> else of this type of design?
>>
>> again, my best regards
>
>I've built multi-processors with both mb and ppc using the Xilinx
>ML401, ML403, ML505, ML506 demo boards. This works fine under multiple
>development environments (virtual pcs with ISE/EDK v9.2 and v10.1).
>
>IMHO the Xilinx docs/tutorials for multi-processors are so thin that
>they are not particularly useful. We have a fairly detailed appnote
>showing how to design/build/test MPSoC using our high-level tools for
>registered users at www.codetronix.com. Go to
>Downloads>AppNotes>MPSoC. This shows how to start from a single-
>processor BSP-wizard-generated xps system, replicate necessary hw
>structures, and download elf files -- it may provide some clues for
>you.
>
>/Per
>
>/Per
>

Hi,

I am new to this site but i found the topic very helpful for me. I jus
need to know if the DDR memory is the only memory that can store MPSo
systems (up to 8 Microblaze systems) on the ML403 board. Can we use th
SRAM too? And how much would it hold (up to how many microblaz
processors)? and in case I am using the FPGA's BRAMs as cache memories
would that affect how many microblaze that could be added?

Thanks a lot,
N

On Jun 10, 5:29*pm, "naim32" <engineer_n...@yahoo.com> wrote:
> >On May 25, 1:08=A0pm, Pablo <pbantu...@gmail.com> wrote:
> >> > I use the MPMC to map memory ports to DDR2 external memory. This
> >> > mechanism has been successfully tested with up to 7 microblazes.
>
> >> > /Per
>
> >> Firstly, thanks a lot.
>
> >> Secondly, I would be grateful if you could tell me if you used XUP
> >> Board and the version of Xilinx Platform Studio. Do you know anything
> >> else of this type of design?
>
> >> again, my best regards
>
> >I've built multi-processors with both mb and ppc using the Xilinx
> >ML401, ML403, ML505, ML506 demo boards. This works fine under multiple
> >development environments (virtual pcs with ISE/EDK v9.2 and v10.1).
>
> >IMHO the Xilinx docs/tutorials for multi-processors are so thin that
> >they are not particularly useful. We have a fairly detailed appnote
> >showing how to design/build/test MPSoC using our high-level tools for
> >registered users atwww.codetronix.com. Go to
> >Downloads>AppNotes>MPSoC. This shows how to start from a single-
> >processor BSP-wizard-generated xps system, replicate necessary hw
> >structures, and download elf files -- it may provide some clues for
> >you.
>
> >/Per
>
> >/Per
>
> Hi,
>
> I am new to this site but i found the topic very helpful for me. I just
> need to know if the DDR memory is the only memory that can store MPSoC
> systems (up to 8 Microblaze systems) on the ML403 board. Can we use the
> SRAM too? And how much would it hold (up to how many microblaze
> processors)? and in case I am using the FPGA's BRAMs as cache memories,
> would that affect how many microblaze that could be added?
>
> Thanks a lot,
> N

No external memories are required by a MB since its elf and stack/heap
can be stored in local BRAM. On large fpgas you can probably squeeze
in at least a dozen MB. If the elf or stack/heap is so large that it
doesn't fit in BRAM, then you can also use external DDR2 or SRAM or
Flash. Using BRAM for other purposes simply reduces the amount
available for MB(s).

The DDR2 uses the Xilinx multiport memory controller (MPMC described
in DS643) with max 8 ports per bank, while the SRAM (or Flash) uses
the Xilinx multi-channel external memory controller (XPS MCH EMC
described in DS575) with max 4 ports. On the Xilinx MLxxx boards there
is only 1 bank of DDR2, SRAM or Flash, while other boards may have
multiple banks.

For higher throughput and higher energy efficiency, it makes sense to
move functionality from sw targets to hw targets.
/Per

>> Hi,
>>
>> I am new to this site but i found the topic very helpful for me.
just
>> need to know if the DDR memory is the only memory that can store MPSoC
>> systems (up to 8 Microblaze systems) on the ML403 board. Can we us
the
>> SRAM too? And how much would it hold (up to how many microblaze
>> processors)? and in case I am using the FPGA's BRAMs as cach
memories,
>> would that affect how many microblaze that could be added?
>>
>> Thanks a lot,
>> N
>
>No external memories are required by a MB since its elf and stack/heap
>can be stored in local BRAM. On large fpgas you can probably squeeze
>in at least a dozen MB. If the elf or stack/heap is so large that it
>doesn't fit in BRAM, then you can also use external DDR2 or SRAM or
>Flash. Using BRAM for other purposes simply reduces the amount
>available for MB(s).
>
>The DDR2 uses the Xilinx multiport memory controller (MPMC described
>in DS643) with max 8 ports per bank, while the SRAM (or Flash) uses
>the Xilinx multi-channel external memory controller (XPS MCH EMC
>described in DS575) with max 4 ports. On the Xilinx MLxxx boards there
>is only 1 bank of DDR2, SRAM or Flash, while other boards may have
>multiple banks.
>
>For higher throughput and higher energy efficiency, it makes sense to
>move functionality from sw targets to hw targets.
>/Per
>

Thanks for the quick feedback, and I am sorry but I am quite new to th
MPSoC domain on the Xilinx boards.

The thing is that I have to use 12 Microblaze processors on my FPGA (ML40
board). The code segment of all of them doesn't fit on the local BRAMs i
the FPGA and that is why I am in need to use external memories to stor
this segment. Also, I wish to use the BRAMs as cache memories for these MB
(I and D cache). My main question is: can I fit 12 Microblaze processors o
external memory (on DDR or SRAM)? Let us say I have one MPMC controlle
with 8 ports, can I add another controller with different start and en
addresses than the previous and then I will have 16 ports?

Thanks in advance
N

On Jun 11, 1:45*am, "naim32" <engineer_n...@yahoo.com> wrote:
> >> Hi,
>
> >> I am new to this site but i found the topic very helpful for me. I
> just
> >> need to know if the DDR memory is the only memory that can store MPSoC
> >> systems (up to 8 Microblaze systems) on the ML403 board. Can we use
> the
> >> SRAM too? And how much would it hold (up to how many microblaze
> >> processors)? and in case I am using the FPGA's BRAMs as cache
> memories,
> >> would that affect how many microblaze that could be added?
>
> >> Thanks a lot,
> >> N
>
> >No external memories are required by a MB since its elf and stack/heap
> >can be stored in local BRAM. On large fpgas you can probably squeeze
> >in at least a dozen MB. If the elf or stack/heap is so large that it
> >doesn't fit in BRAM, then you can also use external DDR2 or SRAM or
> >Flash. Using BRAM for other purposes simply reduces the amount
> >available for MB(s).
>
> >The DDR2 uses the Xilinx multiport memory controller (MPMC described
> >in DS643) with max 8 ports per bank, while the SRAM (or Flash) uses
> >the Xilinx multi-channel external memory controller (XPS MCH EMC
> >described in DS575) with max 4 ports. On the Xilinx MLxxx boards there
> >is only 1 bank of DDR2, SRAM or Flash, while other boards may have
> >multiple banks.
>
> >For higher throughput and higher energy efficiency, it makes sense to
> >move functionality from sw targets to hw targets.
> >/Per
>
> Thanks for the quick feedback, and I am sorry but I am quite new to the
> MPSoC domain on the Xilinx boards.
>
> The thing is that I have to use 12 Microblaze processors on my FPGA (ML403
> board). The code segment of all of them doesn't fit on the local BRAMs in
> the FPGA and that is why I am in need to use external memories to store
> this segment. Also, I wish to use the BRAMs as cache memories for these MBs
> (I and D cache). My main question is: can I fit 12 Microblaze processors on
> external memory (on DDR or SRAM)? Let us say I have one MPMC controller
> with 8 ports, can I add another controller with different start and end
> addresses than the previous and then I will have 16 ports?
>
> Thanks in advance
> N

You can't chain MPMCs -- the SDRAM port is not compatible with the
user port. You can potentially use 8x MB using a MPMC and 4x MB using
MCHEMC, but I've never tried that. I'm also not sure that 12 MB fit on
a ML403 (which is rather small).

Why 12 MB? Moving functionality from sw to hw is normally recommended.

>
>You can't chain MPMCs -- the SDRAM port is not compatible with the
>user port. You can potentially use 8x MB using a MPMC and 4x MB using
>MCHEMC, but I've never tried that. I'm also not sure that 12 MB fit on
>a ML403 (which is rather small).
>
>Why 12 MB? Moving functionality from sw to hw is normally recommended.
>

I have to migrate a system into my board and compare them. If 12 can no
fit, its okay. I have one more question regarding the DDR, I can add up t
8x MBs on the DDR each including I and D cache? I mean, if I enabled the
and D cache for my MBs, still I can fit 8 on the DDR?

Thanks
N

On Jun 11, 12:28*pm, "naim32" <engineer_n...@yahoo.com> wrote:
> >You can't chain MPMCs -- the SDRAM port is not compatible with the
> >user port. You can potentially use 8x MB using a MPMC and 4x MB using
> >MCHEMC, but I've never tried that. I'm also not sure that 12 MB fit on
> >a ML403 (which is rather small).
>
> >Why 12 MB? Moving functionality from sw to hw is normally recommended.
>
> I have to migrate a system into my board and compare them. If 12 can not
> fit, its okay. I have one more question regarding the DDR, I can add up to
> 8x MBs on the DDR each including I and D cache? I mean, if I enabled the I
> and D cache for my MBs, still I can fit 8 on the DDR?
>
> Thanks
> N

I've run 8x MB (without caches), but don't remember if it was a ML4xx
or ML5xx. Allocating (unused) BRAM to caches should be fine.

>
>I've run 8x MB (without caches), but don't remember if it was a ML4xx
>or ML5xx. Allocating (unused) BRAM to caches should be fine.
>

Thank you for the feedback, I will try the system tomorrow and will pos
the results soon... Again Thank you