FPGA Central

Dear Group,

I am using xilinx ise8.2i , xc9536, and I have some questions

One of the documentation files leds.pdf exaplains how much
current will be available when the anode is connected to 5V
and the cathode to the device. However, my situation is
reverse, I want to connect the cathode to 0V and the anode
to the device. Why is this not mentioned?

In document qst.pdf there is a simple simulation of a counter in
page 17. Does this apply only to the vhdl counter, or also to
the verilog counter, because there is also a wizard for
"verilog test fixture" . I tried to follow the instructions for the
"test bench waveform" wizard and the clock picture was
completely black???

Finally, chose the "verilog text fixture" and got the following

initial begin
// Initialize Inputs
c0 = 0;
c1 = 0;

// Wait 100 ns for global reset to finish
#100;

// Add stimulus here

end


What is this global reset, is it something which only belongs in
simulation, or should I have something physical on my
development board?

Two comments:
I really hope that you use a series resistor to limit the current. It
is not good to rely on the output characteritic of the CPLD to limit
the current, and to dissipate the excess power.
Most LEDs are driven in the current sink mode (LED+R connected between
Vcc and the device output. This habit started with TTL circuts, where
the output could sink far more current than it could source. Also, the
Voh was poorly defined, being two diode drops below Vcc. And it still
is, witness the silly 2.4 V specification. I would recomment using
current sink. Perhaps you have to turn the output polarity around.
Remember: there is nothing sacred about active High. It's all in the
mind of the beholder...
Peter Alfke
================

Tonico wrote:
> Dear Group,
>
> I am using xilinx ise8.2i , xc9536, and I have some questions
>
> One of the documentation files leds.pdf exaplains how much
> current will be available when the anode is connected to 5V
> and the cathode to the device. However, my situation is
> reverse, I want to connect the cathode to 0V and the anode
> to the device. Why is this not mentioned?

CPLD's normally drive better to GND, than to Vcc, so that is why most
designs use the Sinking Drive.

You CAN source drive, but you get more voltage drop across the PLD

In both cases, you use a series resistor to define the LED current.

-jg