FPGA Central

Hello,

I have a project where i have to implement a ring oscillator (3 not
gates) using an altera DE2.
But i am confronted to several problems.
The voltage p-p is 128.2 mV and the Vavg is 3.308 V which seems that
quartus has optmised 'a little too much' since i want to see the
delay.

Is there any way to disable the optimisation ? I have read and show on
option 'wire keep_wire', but i did not manage to make it work ... Or
maybe it is another problem.

Thanks for your time, and help

Franck Y <[email protected]> wrote:
> Hello,

> I have a project where i have to implement a ring oscillator (3 not
> gates) using an altera DE2.
> But i am confronted to several problems.
> The voltage p-p is 128.2 mV and the Vavg is 3.308 V which seems that
> quartus has optmised 'a little too much' since i want to see the
> delay.

> Is there any way to disable the optimisation ? I have read and show on
> option 'wire keep_wire', but i did not manage to make it work ... Or
> maybe it is another problem.

What "voltage p-p" is 128.2 mV? Is this something you observe at an output?
What frequency? What output standard? Aren't you overdriving the outputs by
far? Shouldn't you run with a much longer chain? Don't the gate in the
short chain get overloaded?
--
Uwe Bonnes [email protected]

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Franck Y wrote:

> Hello,
>
> I have a project where i have to implement a ring oscillator (3 not
> gates) using an altera DE2.
> But i am confronted to several problems.
> The voltage p-p is 128.2 mV and the Vavg is 3.308 V which seems that
> quartus has optmised 'a little too much' since i want to see the
> delay.
>
> Is there any way to disable the optimisation ? I have read and show on
> option 'wire keep_wire', but i did not manage to make it work ... Or
> maybe it is another problem.
>
> Thanks for your time, and help

Try a longer chain, 3 seems very short, unless they are pin-buffers,
and you should ideally use alternate NOT and NOR gates with a reset
drive, in a ring oscillator.

-jg

On Apr 8, 7:05*pm, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de>
wrote:
> Franck Y <franck...@gmail.com> wrote:
> > Hello,
> > I have a project where i have to implement a ring oscillator (3 not
> > gates) using an altera DE2.
> > But i am confronted to several problems.
> > The voltage p-p is 128.2 mV and the Vavg is 3.308 V which seems that
> > quartus has optmised 'a little too much' since i want to see the
> > delay.
> > Is there any way to disable the optimisation ? I have read and show on
> > option 'wire keep_wire', but i did not manage to make it work ... Or
> > maybe it is another problem.
>
> What "voltage p-p" is 128.2 mV? Is this something you observe at an output?
> What frequency? What output standard? Aren't you overdriving the outputs by
> far? Shouldn't you run with a much longer chain? Don't the gate in the
> short chain get overloaded?
> --
> Uwe Bonnes * * * * * * * *b...@elektron.ikp.physik.tu-darmstadt.de
>
> Institut fuer Kernphysik *Schlossgartenstrasse 9 *64289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

I used an oscilloscope, i tried with a longer chain but apparently it
has no effect,
expect that it has to be odd number of NOT gate.

I do not understand the "Don't the gate in the chain short chain get
overloaded?"

Moreover even if the ring oscillator should not have any power input,
i wanted to put a low voltage( < 1.5V,
but is is another problem since i do not have to possibility to add
external power)

Thanks again for your help

On Apr 8, 7:53*pm, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:
> Franck Y wrote:
> > Hello,
>
> > I have a project where i have to implement a ring oscillator (3 not
> > gates) using an altera DE2.
> > But i am confronted to several problems.
> > The voltage p-p is 128.2 mV and the Vavg is 3.308 V which seems that
> > quartus has optmised 'a little too much' since i want to see the
> > delay.
>
> > Is there any way to disable the optimisation ? I have read and show on
> > option 'wire keep_wire', but i did not manage to make it work ... Or
> > maybe it is another problem.
>
> > Thanks for your time, and help
>
> Try a longer chain, 3 seems very short, unless they are pin-buffers,
> * and you should ideally use alternate NOT and NOR gates with a reset
> drive, in a ring oscillator.
>
> -jg
Hello,

I thought about the reset !

But i do have to put a VCC or a ground ? But i do that, my result will
be wrong
F

Franck Y <[email protected]> wrote:
...
> I do not understand the "Don't the gate in the chain short chain get
> overloaded?"
....
You probably drive the gates in the linear region, where a lot of current is
flowing through the upper PMOS and lower NMos transistor. While this current
also flows during normal switching, this switching happens at a lower
frequency, resulting in lower effective current flow through tghe inverter.

--
Uwe Bonnes [email protected]

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

On Apr 8, 6:53 pm, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:
> Franck Y wrote:
> > Hello,
>
> > I have a project where i have to implement a ring oscillator (3 not
> > gates) using an altera DE2.
> > But i am confronted to several problems.
> > The voltage p-p is 128.2 mV and the Vavg is 3.308 V which seems that
> > quartus has optmised 'a little too much' since i want to see the
> > delay.
>
> > Is there any way to disable the optimisation ? I have read and show on
> > option 'wire keep_wire', but i did not manage to make it work ... Or
> > maybe it is another problem.
>
> > Thanks for your time, and help
>
> Try a longer chain, 3 seems very short, unless they are pin-buffers,
> and you should ideally use alternate NOT and NOR gates with a reset
> drive, in a ring oscillator.
>
> -jg

3 is probably fine, if they are placed fairly far apart. Quartus is
probably placing them in the same LAB, where the delay between flops
will be exceedingly small. Manually placing them in the corners should
increase the delay long enough to actually see some ringing. Turn on
logic lock for the path, and it should be very predictable between
fittings.

On 9 Apr., 00:52, Franck Y <franck...@gmail.com> wrote:
> I have a project where i have to implement a ring oscillator (3 not
> gates) [...]
> which seems that
> quartus has optmised 'a little too much' since i want to see the
> delay.

You can't even really call that optimization.
You seen, in an FPGA you do not have individual not and nor gates.
You have 4 input lookup tables. Even in an ASIC technology there is
a technology mapping step involved, that tries to find a
representation
in the target technology for your technology independant
specification.

While it would be possible to map your desing 1 to 1 to the FPGA
technology
in general that is not possible, so the tool does not even try.
Instead it is
looking for netlist portion (not individual gates) that can be
represented by
the FPGAs ressources.

In your case it finds an obvious match: The whole circuit can be
represented by
a single LUT. Of course it chooses that representation. This is not an
overly aggressive
optimization, it is a necessary step to find a realizable netlist at
all.

The solution to your problem is a technology dependant representation:
Instantiate
LUT primitives. You can even manually place them to increase the
delay.

Kolja Sulimma