FPGA Central

Hi there,

I have a question regarding clock deskewing. My design has a sub
module that gets its clock signal from a regional clock pin, however,
the clock skew is too large and causing timing violations.

I read about something on DCM and thought about using it to deskew
this regional clock, but it seems to me that DCM can only be used in
conjunction with global clock lines. The board layout is fixed, which
means no way I can use a global clock line for this signal, have to
live with it.

Has anybody experience with regional clock deskewing?

Thanks a lot!

On Nov 24, 8:07*am, bonnerfme <xiaoling...@fme.fujitsu.com> wrote:
> Hi there,
>
> I have a question regarding clock deskewing. My design has a sub
> module that gets its clock signal from a regional clock pin, however,
> the clock skew is too large and causing timing violations.
>
> I read about something on DCM and thought about using it to deskew
> this regional clock, but it seems to me that DCM can only be used in
> conjunction with global clock lines. The board layout is fixed, which
> means no way I can use a global clock line for this signal, have to
> live with it.
>
> Has anybody experience with regional clock deskewing?
>
> Thanks a lot!

Are you sure you mean deskew? That is a routing issue. I don't
see how a DCM would help unless you're talking about the skew
between the regional clock and some other clock.

Confused,
Gabor

a,

The DCM has a fixed phase shift feature, so you can "move" the clock
outputs, anywhere you want, from 0 to 360 degrees, with 1/256
resolution.

Austin

On Nov 24, 2:49*pm, Gabor <ga...@alacron.com> wrote:
> On Nov 24, 8:07*am, bonnerfme <xiaoling...@fme.fujitsu.com> wrote:
>
> > Hi there,
>
> > I have a question regarding clock deskewing. My design has a sub
> > module that gets its clock signal from a regional clock pin, however,
> > the clock skew is too large and causing timing violations.
>
> > I read about something on DCM and thought about using it to deskew
> > this regional clock, but it seems to me that DCM can only be used in
> > conjunction with global clock lines. The board layout is fixed, which
> > means no way I can use a global clock line for this signal, have to
> > live with it.
>
> > Has anybody experience with regional clock deskewing?
>
> > Thanks a lot!
>
> Are you sure you mean deskew? *That is a routing issue. *I don't
> see how a DCM would help unless you're talking about the skew
> between the regional clock and some other clock.
>
> Confused,
> Gabor

Hi Gabor, you're right, this is a routing issue.I meant the skew just
on this regional clock, not the skew between it and some other clock.
Maybe DCM is not the right thing to go for, I'm no sure, please advise
what is the correct thing I should look into.

BR

bonnerfme wrote:

> My design has a sub
> module that gets its clock signal from a regional clock pin, however,
> the clock skew is too large and causing timing violations.

You could make a synchronous divide by n +- cal ppm
using a phase accumulator. A host computer
could do the time error to delta cal calculation
if the integrated time error can be measured.

-- Mike Treseler

input violations, output violations, or flop/flop violations?

Is your clock being routed using logic routing resources or a dedicated
clock resource? Your clock needs to go on a global clock line if it isn't
there already. It's hard to meet timing with clocks on logic routing, maybe
with some careful hand placement you could do it.

--steve

"bonnerfme" <xiaoling.li@fme.fujitsu.com> wrote in message
news:3a29c0c0-14cf-4289-92ee-aaf972ef2af7@t18g2000vbj.googlegroups.com...
: Hi there,
:
: I have a question regarding clock deskewing. My design has a sub
: module that gets its clock signal from a regional clock pin, however,
: the clock skew is too large and causing timing violations.
:
: I read about something on DCM and thought about using it to deskew
: this regional clock, but it seems to me that DCM can only be used in
: conjunction with global clock lines. The board layout is fixed, which
: means no way I can use a global clock line for this signal, have to
: live with it.
:
: Has anybody experience with regional clock deskewing?
:
: Thanks a lot!

On Nov 24, 12:31*pm, bonnerfme <xiaoling...@fme.fujitsu.com> wrote:
> On Nov 24, 2:49*pm, Gabor <ga...@alacron.com> wrote:
>
>
>
> > On Nov 24, 8:07*am, bonnerfme <xiaoling...@fme.fujitsu.com> wrote:
>
> > > Hi there,
>
> > > I have a question regarding clock deskewing. My design has a sub
> > > module that gets its clock signal from a regional clock pin, however,
> > > the clock skew is too large and causing timing violations.
>
> > > I read about something on DCM and thought about using it to deskew
> > > this regional clock, but it seems to me that DCM can only be used in
> > > conjunction with global clock lines. The board layout is fixed, which
> > > means no way I can use a global clock line for this signal, have to
> > > live with it.
>
> > > Has anybody experience with regional clock deskewing?
>
> > > Thanks a lot!
>
> > Are you sure you mean deskew? *That is a routing issue. *I don't
> > see how a DCM would help unless you're talking about the skew
> > between the regional clock and some other clock.
>
> > Confused,
> > Gabor
>
> Hi Gabor, you're right, this is a routing issue.I meant the skew just
> on this regional clock, not the skew between it and some other clock.
> Maybe DCM is not the right thing to go for, I'm no sure, please advise
> what is the correct thing I should look into.
>
> BR

What kind of device are you using? Is this "Regional clock"
driven by a dedicated clock buffer like a BUFR in the Virtex 5?
Or do you mean you're using non-global routing resources for
the clock?