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  #1 (permalink)  
Old 03-12-2008, 05:54 AM
[email protected]
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Default Design complexity in Logic cells - Virtex-5 FPGA

Hi,
Some IP vendors gives the complexity of the device in terms of "LCs
(Logic Cells)".
How can I calcuate Logic cells from information available in Map
report?

**********
Logic Utilization:
Number of Slice Flip Flops: 4,288 out of 84,352 5%
Number of 4 input LUTs: 7,880 out of 84,352 9%
Logic Distribution:
Number of occupied Slices: 5,150 out of
42,176 12%
Number of Slices containing only related logic: 5,150 out of
5,150 100%
Number of Slices containing unrelated logic: 0 out of
5,150 0%
*See NOTES below for an explanation of the effects of unrelated
logic
Total Number of 4 input LUTs: 8,119 out of 84,352 9%
Number used as logic: 7,880
Number used as a route-thru: 159
Number used for Dual Port RAMs: 80
(Two LUTs used per Dual Port RAM)
Number of bonded IOBs: 500 out of 576 86%
Number of BUFG/BUFGCTRLs: 5 out of 32 15%
Number used as BUFGs: 5
Number used as BUFGCTRLs: 0
**************

Thanks in advance,
Muthu
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  #2 (permalink)  
Old 03-12-2008, 11:19 AM
Kolja Sulimma
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Default Re: Design complexity in Logic cells - Virtex-5 FPGA

Until recently comparing 4-LUTs was the way to go. (Except for
pathological cases)
Now Virtex-5 with its 6-LUTs makes life more complicated.

Kolja

On 12 Mrz., 04:54, muthu...@gmail.com wrote:
> Hi,
> Some IP vendors gives the complexity of the device in terms of "LCs
> (Logic Cells)".
> How can I calcuate Logic cells from information available in Map
> report?
>
> **********
> Logic Utilization:
> Number of Slice Flip Flops: 4,288 out of 84,352 5%
> Number of 4 input LUTs: 7,880 out of 84,352 9%
> Logic Distribution:
> Number of occupied Slices: 5,150 out of
> 42,176 12%
> Number of Slices containing only related logic: 5,150 out of
> 5,150 100%
> Number of Slices containing unrelated logic: 0 out of
> 5,150 0%
> *See NOTES below for an explanation of the effects of unrelated
> logic
> Total Number of 4 input LUTs: 8,119 out of 84,352 9%
> Number used as logic: 7,880
> Number used as a route-thru: 159
> Number used for Dual Port RAMs: 80
> (Two LUTs used per Dual Port RAM)
> Number of bonded IOBs: 500 out of 576 86%
> Number of BUFG/BUFGCTRLs: 5 out of 32 15%
> Number used as BUFGs: 5
> Number used as BUFGCTRLs: 0
> **************
>
> Thanks in advance,
> Muthu


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  #3 (permalink)  
Old 03-13-2008, 06:29 AM
[email protected]
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Default Re: Design complexity in Logic cells - Virtex-5 FPGA

Using registers is probably the best way to go. You avoid the
marketing mathematics of any given vendor, and to be honest with fmax
being primarily limited by routing now, it seems that designs have
very few levels of logic meaning the logic:register ratio is close to
1:1 for high performance IP.
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  #4 (permalink)  
Old 03-13-2008, 11:08 AM
Kolja Sulimma
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Default Re: Design complexity in Logic cells - Virtex-5 FPGA

On 13 Mrz., 05:29, bku...@engineer.com wrote:
> meaning the logic:register ratio is close to
> 1:1 for high performance IP.


As a counter example: The ration is almost 2:1 in the example given
by the OP.

Kolja Sulimma
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  #5 (permalink)  
Old 03-13-2008, 06:51 PM
Mike Treseler
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Default Re: Design complexity in Logic cells - Virtex-5 FPGA

[email protected] wrote:
> Some IP vendors gives the complexity of the device in terms of "LCs
> (Logic Cells)".
> How can I calcuate Logic cells from information available in Map
> report?


Ask the vendor for LUTs and Flops stats for your device.
If they can't tell you, find another vendor.

-- Mike Treseler
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  #6 (permalink)  
Old 03-15-2008, 04:30 AM
jtw
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Default Re: Design complexity in Logic cells - Virtex-5 FPGA

6-LUTs? Sounds somthing like ORCA... (ATT -> Lucent -> Lattice)

JTW

"Kolja Sulimma" <[email protected]> wrote in message
news:[email protected]..
> Until recently comparing 4-LUTs was the way to go. (Except for
> pathological cases)
> Now Virtex-5 with its 6-LUTs makes life more complicated.
>
> Kolja
>
> On 12 Mrz., 04:54, muthu...@gmail.com wrote:
>> Hi,
>> Some IP vendors gives the complexity of the device in terms of "LCs
>> (Logic Cells)".
>> How can I calcuate Logic cells from information available in Map
>> report?
>>
>> **********
>> Logic Utilization:
>> Number of Slice Flip Flops: 4,288 out of 84,352 5%
>> Number of 4 input LUTs: 7,880 out of 84,352 9%
>> Logic Distribution:
>> Number of occupied Slices: 5,150 out of
>> 42,176 12%
>> Number of Slices containing only related logic: 5,150 out of
>> 5,150 100%
>> Number of Slices containing unrelated logic: 0 out of
>> 5,150 0%
>> *See NOTES below for an explanation of the effects of unrelated
>> logic
>> Total Number of 4 input LUTs: 8,119 out of 84,352 9%
>> Number used as logic: 7,880
>> Number used as a route-thru: 159
>> Number used for Dual Port RAMs: 80
>> (Two LUTs used per Dual Port RAM)
>> Number of bonded IOBs: 500 out of 576 86%
>> Number of BUFG/BUFGCTRLs: 5 out of 32 15%
>> Number used as BUFGs: 5
>> Number used as BUFGCTRLs: 0
>> **************
>>
>> Thanks in advance,
>> Muthu

>



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