FPGA Central

Hi, there:

I tried one simulation with the following parameters to derive a 36MHz from
40MHz crystal...
It works in simulation, but does it work in Virtex-2 with speed grade of 6?
I am cautious as
40 * 9 makes 360MHz and it is beyond the Virtex-2's DCM timing
specification.

defparam DCM1.CLKFX_DIVIDE = 10;
defparam DCM1.CLKFX_MULTIPLY = 9;

I also tried to use a state machine to divide crystal into 4MHz and then
multiply by 9, but it Model-Sim
complained the input clock jitter was beyond 1ns...

How may I do this task?

Thanks for your advice...
Kelvin

Hi Kelvin,
This should work fine, the DCM multiplies and divides at the same time (in
simplistic terms) so the spec isn't exceeded.
cheers, Syms.

"Kelvin @ SG" <[email protected]> wrote in message
news:bud50h$9ab$[email protected]..
> Hi, there:
>
> I tried one simulation with the following parameters to derive a 36MHz
from
> 40MHz crystal...
> It works in simulation, but does it work in Virtex-2 with speed grade of
6?
> I am cautious as
> 40 * 9 makes 360MHz and it is beyond the Virtex-2's DCM timing
> specification.
>
> defparam DCM1.CLKFX_DIVIDE = 10;
> defparam DCM1.CLKFX_MULTIPLY = 9;
>
> I also tried to use a state machine to divide crystal into 4MHz and then
> multiply by 9, but it Model-Sim
> complained the input clock jitter was beyond 1ns...
>
> How may I do this task?
>
> Thanks for your advice...
> Kelvin
>
>
>
>

"Kelvin @ SG" <[email protected]> wrote in message news:<bud50h$9ab$[email protected]>...
> Hi, there:
>
> I tried one simulation with the following parameters to derive a 36MHz from
> 40MHz crystal...
> It works in simulation, but does it work in Virtex-2 with speed grade of 6?
> I am cautious as
> 40 * 9 makes 360MHz and it is beyond the Virtex-2's DCM timing
> specification.
>
> defparam DCM1.CLKFX_DIVIDE = 10;
> defparam DCM1.CLKFX_MULTIPLY = 9;

RTFM, RTFM, RTFM
there is somewhere a notice in datasheets that the DCM can be used
in such situation where the virtual CLK is way beyound operating
frequency, the DCM will still work.

So you should be safe, using the DCM with those parameters as given.

Antti
http://xilinx.openchip.org

Just to confirm it officially:
In frequency synthesis mode, M/D is done as a combined mathematical
operation. Therefore it is irrelevant that the multiplication by itself
might exceed the max frequency. I remember publishing this in several
places, but cannot find it right now. It is one of the major nice
features of the DCM.

Peter Alfke, Xilinx Applications
================
Antti Lukats wrote:
>
> "
> RTFM, RTFM, RTFM
> there is somewhere a notice in datasheets that the DCM can be used
> in such situation where the virtual CLK is way beyound operating
> frequency, the DCM will still work.
>
> So you should be safe, using the DCM with those parameters as given.
>
>

See page 54, second paragraph in XAPP462: Using Digital Clock Managers
(DCMs) in Spartan-3 FPGAs.
http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf

--------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC

"Peter Alfke" <[email protected]> wrote in message
news:[email protected]..
> Just to confirm it officially:
> In frequency synthesis mode, M/D is done as a combined mathematical
> operation. Therefore it is irrelevant that the multiplication by itself
> might exceed the max frequency. I remember publishing this in several
> places, but cannot find it right now. It is one of the major nice
> features of the DCM.
>
> Peter Alfke, Xilinx Applications
> ================
> Antti Lukats wrote:
> >
> > "
> > RTFM, RTFM, RTFM
> > there is somewhere a notice in datasheets that the DCM can be used
> > in such situation where the virtual CLK is way beyound operating
> > frequency, the DCM will still work.
> >
> > So you should be safe, using the DCM with those parameters as given.
> >
> >

Actually, this is close to correct. Nothing is "multiplied". The 40
MHz reference clock will be divided by 10 to reach 4 MHz. The output
will be divided by 9 to give 4 MHz. The two signals at 4 Mhz are
compared at the phase comparator to control the oscillator. But you do
have to assure that 4 MHz is within the range that the phase comparator
can work.


symon wrote:
>
> Hi Kelvin,
> This should work fine, the DCM multiplies and divides at the same time (in
> simplistic terms) so the spec isn't exceeded.
> cheers, Syms.
>
> "Kelvin @ SG" <[email protected]> wrote in message
> news:bud50h$9ab$[email protected]..
> > Hi, there:
> >
> > I tried one simulation with the following parameters to derive a 36MHz
> from
> > 40MHz crystal...
> > It works in simulation, but does it work in Virtex-2 with speed grade of
> 6?
> > I am cautious as
> > 40 * 9 makes 360MHz and it is beyond the Virtex-2's DCM timing
> > specification.
> >
> > defparam DCM1.CLKFX_DIVIDE = 10;
> > defparam DCM1.CLKFX_MULTIPLY = 9;
> >
> > I also tried to use a state machine to divide crystal into 4MHz and then
> > multiply by 9, but it Model-Sim
> > complained the input clock jitter was beyond 1ns...
> >
> > How may I do this task?
> >
> > Thanks for your advice...
> > Kelvin

Close, but no cigar.
You can use any combination of input frequency, M, and D, as long as
the output frequency is above 24 MHz, and does not exceed the max,
somewhere around 400 MHz.( M and D each cannot exceed 32 ).
The phase comparator is never the limitation.
Peter Alfke, Xilinx Applications

Ralph Malph wrote:
>
> Actually, this is close to correct. Nothing is "multiplied". The 40
> MHz reference clock will be divided by 10 to reach 4 MHz. The output
> will be divided by 9 to give 4 MHz. The two signals at 4 Mhz are
> compared at the phase comparator to control the oscillator. But you do
> have to assure that 4 MHz is within the range that the phase comparator
> can work.
>
> symon wrote:
> >
> > Hi Kelvin,
> > This should work fine, the DCM multiplies and divides at the same time (in
> > simplistic terms) so the spec isn't exceeded.
> > cheers, Syms.
> >
> > "Kelvin @ SG" <[email protected]> wrote in message
> > news:bud50h$9ab$[email protected]..
> > > Hi, there:
> > >
> > > I tried one simulation with the following parameters to derive a 36MHz
> > from
> > > 40MHz crystal...
> > > It works in simulation, but does it work in Virtex-2 with speed grade of
> > 6?
> > > I am cautious as
> > > 40 * 9 makes 360MHz and it is beyond the Virtex-2's DCM timing
> > > specification.
> > >
> > > defparam DCM1.CLKFX_DIVIDE = 10;
> > > defparam DCM1.CLKFX_MULTIPLY = 9;
> > >
> > > I also tried to use a state machine to divide crystal into 4MHz and then
> > > multiply by 9, but it Model-Sim
> > > complained the input clock jitter was beyond 1ns...
> > >
> > > How may I do this task?
> > >
> > > Thanks for your advice...
> > > Kelvin

Perhaps I should quote the passage:

"
Two attributes, set at design time, control the synthesized output
frequency. The CLKIN clock input is multiplied the fraction formed by
CLKFX_MULTIPLY as the numerator and CLKFX_DIVIDE as the denominator. For
example, to create a 155MHz output using a 75MHz CLKIN input, the Frequency
Synthesizer multiplies CLKIN by the fraction 31/15. Note that it does not
multiply CLKIN by 31 first, then divide by the result by 15. Multiplying
CLKIN by 31 would result in a 2.325GHz output frequency-well outside the
frequency range of the Spartan-3 DCM."

"Steven K. Knapp" <[email protected]> wrote in message
news:buh78s$[email protected]..
> See page 54, second paragraph in XAPP462: Using Digital Clock Managers
> (DCMs) in Spartan-3 FPGAs.
> http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf
>
> --------------------------------
> Steven K. Knapp
> Applications Manager, Xilinx Inc.
> General Products Division
> Spartan-3/II/IIE FPGAs
> http://www.xilinx.com/spartan3
> ---------------------------------
> Spartan-3: Make it Your ASIC
>
> "Peter Alfke" <[email protected]> wrote in message
> news:[email protected]..
> > Just to confirm it officially:
> > In frequency synthesis mode, M/D is done as a combined mathematical
> > operation. Therefore it is irrelevant that the multiplication by itself
> > might exceed the max frequency. I remember publishing this in several
> > places, but cannot find it right now. It is one of the major nice
> > features of the DCM.
> >
> > Peter Alfke, Xilinx Applications
> > ================
> > Antti Lukats wrote:
> > >
> > > "
> > > RTFM, RTFM, RTFM
> > > there is somewhere a notice in datasheets that the DCM can be used
> > > in such situation where the virtual CLK is way beyound operating
> > > frequency, the DCM will still work.
> > >
> > > So you should be safe, using the DCM with those parameters as given.
> > >
> > >
>
>

Hi, All:

Thank you very much for your replies. I understand it now and I will try it
out.

Best Regards,
Kelvin



Steven K. Knapp <[email protected]> wrote in message
news:buhvu1$[email protected]..
> Perhaps I should quote the passage:
>
> "
> Two attributes, set at design time, control the synthesized output
> frequency. The CLKIN clock input is multiplied the fraction formed by
> CLKFX_MULTIPLY as the numerator and CLKFX_DIVIDE as the denominator. For
> example, to create a 155MHz output using a 75MHz CLKIN input, the
Frequency
> Synthesizer multiplies CLKIN by the fraction 31/15. Note that it does not
> multiply CLKIN by 31 first, then divide by the result by 15. Multiplying
> CLKIN by 31 would result in a 2.325GHz output frequency-well outside the
> frequency range of the Spartan-3 DCM."
>
> "Steven K. Knapp" <[email protected]> wrote in message
> news:buh78s$[email protected]..
> > See page 54, second paragraph in XAPP462: Using Digital Clock Managers
> > (DCMs) in Spartan-3 FPGAs.
> > http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf
> >
> > --------------------------------
> > Steven K. Knapp
> > Applications Manager, Xilinx Inc.
> > General Products Division
> > Spartan-3/II/IIE FPGAs
> > http://www.xilinx.com/spartan3
> > ---------------------------------
> > Spartan-3: Make it Your ASIC
> >
> > "Peter Alfke" <[email protected]> wrote in message
> > news:[email protected]..
> > > Just to confirm it officially:
> > > In frequency synthesis mode, M/D is done as a combined mathematical
> > > operation. Therefore it is irrelevant that the multiplication by
itself
> > > might exceed the max frequency. I remember publishing this in several
> > > places, but cannot find it right now. It is one of the major nice
> > > features of the DCM.
> > >
> > > Peter Alfke, Xilinx Applications
> > > ================
> > > Antti Lukats wrote:
> > > >
> > > > "
> > > > RTFM, RTFM, RTFM
> > > > there is somewhere a notice in datasheets that the DCM can be used
> > > > in such situation where the virtual CLK is way beyound operating
> > > > frequency, the DCM will still work.
> > > >
> > > > So you should be safe, using the DCM with those parameters as given.
> > > >
> > > >
> >
> >
>
>