FPGA Central

I am wondering how does John implement dual bank controller in
Spartan-3A

http://www.enterpoint.co.uk/oem_indu...ollybush2.html

the above includes the link to the S3A product with DDR3 memories

what makes me wonder is that Xilinx says

http://www.xilinx.com/prs_rls/2007/s..._ddr3sdram.htm

that Virtex-5 are the first FPGA's in production supporting DDR3

if enternpoint has proven DDR3 interface with DDR3 this should
be big news? Like written bold on Xilinx

first company to offer DDR3 support in low cost FPGA family?

Antti

Hello Antti,
on the webpage is a .ucf file available, but this contains NOT the
DDR3-SDRAM pins.

You are right, spartan-3A DSP does not support DDR3-Voltage Levels.

Use the SSTL18_[I,II] at VCCO=1.5V and Vref=0,75V should be possible,
but nobody guarantees the IO-Timing and Voltage Levels.

But there is a second challenge. The maximal clock cycle with DDR3-
SDRAM DLL enabled is 3.3 ns (~300 Mhz) this should be above any the
Spartan-3A Memory-Controllers.

Micron Datasheet:
http://download.micron.com/pdf/datas...R3%20SDRAM.pdf


This DLL can disabled, but the relationchip between clk and data
output delay is lost. Second you must disable the ODT (On Die
Termination).

In my opinion, the SDRAM-Controller is the big challenge. So we wait
for a DDR3-Controller from enterpoint.

Daniel

On 16 Feb., 16:54, Antti <Antti.Luk...@googlemail.com> wrote:
> I am wondering how does John implement dual bank controller in
> Spartan-3A
>
> http://www.enterpoint.co.uk/oem_indu...ollybush2.html
>
> the above includes the link to the S3A product with DDR3 memories
>
> what makes me wonder is that Xilinx says
>
> http://www.xilinx.com/prs_rls/2007/s..._ddr3sdram.htm
>
> that Virtex-5 are the first FPGA's in production supporting DDR3
>
> if enternpoint has proven DDR3 interface with DDR3 this should
> be big news? Like written bold on Xilinx
>
> first company to offer DDR3 support in low cost FPGA family?
>
> Antti

"[email protected]" <[email protected]> wrote:

>Hello Antti,
>on the webpage is a .ucf file available, but this contains NOT the
>DDR3-SDRAM pins.
>
>You are right, spartan-3A DSP does not support DDR3-Voltage Levels.
>
>Use the SSTL18_[I,II] at VCCO=1.5V and Vref=0,75V should be possible,
>but nobody guarantees the IO-Timing and Voltage Levels.
>
>But there is a second challenge. The maximal clock cycle with DDR3-
>SDRAM DLL enabled is 3.3 ns (~300 Mhz) this should be above any the
>Spartan-3A Memory-Controllers.
>
>Micron Datasheet:
>http://download.micron.com/pdf/datas...R3%20SDRAM.pdf
>
>
>This DLL can disabled, but the relationchip between clk and data
>output delay is lost. Second you must disable the ODT (On Die
>Termination).

If you disable the DLL, the clock range of DDR3 is very wide. Actually
much wider when using DDR or DDR2 memory. So it makes perfect sense to
use DDR3 on an FPGA because its lower power and easier to design and
still have dual data rate memory. Running it at 80MHz or 100MHz is
very feasible IMHO.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------

On Feb 17, 6:51*pm, n...@puntnl.niks (Nico Coesel) wrote:
> "koethe.daniel...@googlemail.com" <dkoe...@web.de> wrote:
> >Hello Antti,
> >on the webpage is a .ucf file available, but this contains NOT the
> >DDR3-SDRAM pins.
>
> >You are right, spartan-3A DSP does not support DDR3-Voltage Levels.
>
> >Use the SSTL18_[I,II] at VCCO=1.5V and Vref=0,75V should be possible,
> >but nobody guarantees the IO-Timing and Voltage Levels.
>
> >But there is a second challenge. The maximal clock cycle with DDR3-
> >SDRAM DLL enabled is 3.3 ns (~300 Mhz) this should be above any the
> >Spartan-3A Memory-Controllers.
>
> >Micron Datasheet:
> >http://download.micron.com/pdf/datas...%20DDR3%20SDRA...
>
> >This DLL can disabled, but the relationchip between clk and data
> >output delay is lost. Second you must disable the ODT (On Die
> >Termination).
>
> If you disable the DLL, the clock range of DDR3 is very wide. Actually
> much wider when using DDR or DDR2 memory. So it makes perfect sense to
> use DDR3 on an FPGA because its lower power and easier to design and
> still have dual data rate memory. Running it at 80MHz or 100MHz is
> very feasible IMHO.
>
> --
> Failure does not prove something is impossible, failure simply
> indicates you are not using the right tools...
> * * * * * * * * * * *"If it doesn't fit, use a bigger hammer!"
> --------------------------------------------------------------

hmm

enterpoint Press Release promotes the HB2 for:
"aircraft, automotive, shipping and rail applications."

would you recommend to design in a product
with DDR3 and disabled DLL for aerospace use?

for development it sure may be ok.

Antti

Antti <[email protected]> wrote:

>On Feb 17, 6:51=A0pm, n...@puntnl.niks (Nico Coesel) wrote:
>> "koethe.daniel...@googlemail.com" <dkoe...@web.de> wrote:
>> >Hello Antti,
>> >on the webpage is a .ucf file available, but this contains NOT the
>> >DDR3-SDRAM pins.
>>
>> >You are right, spartan-3A DSP does not support DDR3-Voltage Levels.
>>
>> >Use the SSTL18_[I,II] at VCCO=3D1.5V and Vref=3D0,75V should be possible=
>,
>> >but nobody guarantees the IO-Timing and Voltage Levels.
>>
>> >But there is a second challenge. The maximal clock cycle with DDR3-
>> >SDRAM DLL enabled is 3.3 ns (~300 Mhz) this should be above any the
>> >Spartan-3A Memory-Controllers.
>>
>> >Micron Datasheet:
>> >http://download.micron.com/pdf/datas...%20DDR3%20SDRA...
>>
>> >This DLL can disabled, but the relationchip between clk and data
>> >output delay is lost. Second you must disable the ODT (On Die
>> >Termination).
>>
>> If you disable the DLL, the clock range of DDR3 is very wide. Actually
>> much wider when using DDR or DDR2 memory. So it makes perfect sense to
>> use DDR3 on an FPGA because its lower power and easier to design and
>> still have dual data rate memory. Running it at 80MHz or 100MHz is
>> very feasible IMHO.
>>
>> --------------------------------------------------------------
>
>hmm
>
>enterpoint Press Release promotes the HB2 for:
>"aircraft, automotive, shipping and rail applications."
>
>would you recommend to design in a product
>with DDR3 and disabled DLL for aerospace use?

As long as it meets timing and its operation is more or less
guaranteed by the manufacturor. Micron is not recommending operating
the memory with the DLL off, but they do specify the timing. Samsung
does the same. It seems the DDR3 devices operate similar with some
timing restrictions when the DLL is off. The biggest problem seems
that Jedec didn't specify the timing requirements with the DLL off.
This potentially kills interoperability between memories.

Back to the real world. Some DDR3 controllers require to read/write
the memory before enabling the DLL for timing calibrations. In other
words if the memory can't be read/written reliably with the DLL off
the memory might not work in every situation.

But lets see what John has to say about this.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------

I'll start by saying we are still only letting HB2 out to selected
customers on an early release program. It's a very complex board to
fully design test and we are also suffering an extremely large work
overload virtually since we released this product and we are behind
schedule doing things with this board.

The DDR3 is one few remaining areas we have to complete testing on and
it was a late addition to the design replacing a DDR2 memory stack. I
have a realistic expectation that the DDR3 will work. We are not
aiming to run at full speed but at a speed sufficient for our intended
use that of supporting a MicroBlaze design. The DDR3 offers the
highest density and lowest power for the application. If by chance we
are wromg on the way we intend to achive the working DDR3 the design
will fall back to the original DDR2 for the main build batch but I
don't expect that to be necessary. Historically we have always led in
technology and with a very high success rate at making the new
technology work.

On Antti's point about aerospace etc. there are a lot of applications
there that are not safety critical e.g. entertainment systems where
new technology isn't always a barrier. That aside all technology was
new at some point and eventually got adopted and is flying now. We
also do a lot of derivative designs from the public development boards
and the development boards mainly act as showcases as to what can be
done. A particular customer can always ask SRAM or SDRAM instead on
their custom if they don't like DDR3. If they are prepared to pay the
NRE and we can physically get it on the board they can have what they
want.

We do have a lot of things planned for the Hollybush range and HB2 is
only a taster of what we have planned.

I will also say we have a reasonable number of cards flying around in
helicoopters and other aircraft without issue.

Assuming that this all works ok we will be releasing a DDR3 core as a
product and even if it's not used on HB2 we have plenty of boards
coming that will support the technology. We have a big year to
celebrate this year and as part of that celebration we will release a
record number of new products. I will be talking more about this in
our next newsletter to customers and maybe letting a one or two
pleasant surprises out of the bag.

John Adair
Enterpoint Ltd.

On 17 Feb, 23:06, n...@puntnl.niks (Nico Coesel) wrote:
> Antti <Antti.Luk...@googlemail.com> wrote:
> >On Feb 17, 6:51=A0pm, n...@puntnl.niks (Nico Coesel) wrote:
> >> "koethe.daniel...@googlemail.com" <dkoe...@web.de> wrote:
> >> >Hello Antti,
> >> >on the webpage is a .ucf file available, but this contains NOT the
> >> >DDR3-SDRAM pins.
>
> >> >You are right, spartan-3A DSP does not support DDR3-Voltage Levels.
>
> >> >Use the SSTL18_[I,II] at VCCO=3D1.5V and Vref=3D0,75V should be possible=
> >,
> >> >but nobody guarantees the IO-Timing and Voltage Levels.
>
> >> >But there is a second challenge. The maximal clock cycle with DDR3-
> >> >SDRAM DLL enabled is 3.3 ns (~300 Mhz) this should be above any the
> >> >Spartan-3A Memory-Controllers.
>
> >> >Micron Datasheet:
> >> >http://download.micron.com/pdf/datas...%20DDR3%20SDRA....
>
> >> >This DLL can disabled, but the relationchip between clk and data
> >> >output delay is lost. Second you must disable the ODT (On Die
> >> >Termination).
>
> >> If you disable the DLL, the clock range of DDR3 is very wide. Actually
> >> much wider when using DDR or DDR2 memory. So it makes perfect sense to
> >> use DDR3 on an FPGA because its lower power and easier to design and
> >> still have dual data rate memory. Running it at 80MHz or 100MHz is
> >> very feasible IMHO.
>
> >> --------------------------------------------------------------
>
> >hmm
>
> >enterpoint Press Release promotes the HB2 for:
> >"aircraft, automotive, shipping and rail applications."
>
> >would you recommend to design in a product
> >with DDR3 and disabled DLL for aerospace use?
>
> As long as it meets timing and its operation is more or less
> guaranteed by the manufacturor. Micron is not recommending operating
> the memory with the DLL off, but they do specify the timing. Samsung
> does the same. It seems the DDR3 devices operate similar with some
> timing restrictions when the DLL is off. The biggest problem seems
> that Jedec didn't specify the timing requirements with the DLL off.
> This potentially kills interoperability between memories.
>
> Back to the real world. Some DDR3 controllers require to read/write
> the memory before enabling the DLL for timing calibrations. In other
> words if the memory can't be read/written reliably with the DLL off
> the memory might not work in every situation.
>
> But lets see what John has to say about this.
>
> --
> Failure does not prove something is impossible, failure simply
> indicates you are not using the right tools...
> * * * * * * * * * * *"If it doesn't fit, use a bigger hammer!"
> --------------------------------------------------------------- Hide quoted text -
>
> - Show quoted text -