DDR2 w/ MIG on Xilinx ML501 Board

Hello -

I am trying to use the Xilinx MIG version 1.72 to generate a working
interface for the DDR2 memory on the Xilinx ML501 eval board. I am
having a bit of trouble.

I am able to simulate the controller and testbench just fine using
ModelSim, but seem to be having issues getting it to work in hardware.
At the moment, I am simply checking the output of the phy_init_done
signal, which does not go high at any point, which indicates a problem
to me. I have not yet been able to delve much deeper into where things
are getting stuck.

I plan to use ChipScope to try to see what is going on, but I wonder
before I get too far, if anybody else has tried a similar
configuration? What experiences (good/bad) have people had with the
MIG and Virtex-5 DDR2 designs? It would make me feel better if
somebody out there had gotten it to work - it sounds like - from
reading this group at least, that there are no shortage of issues with
this stuff.

Thanks,
Ben

On Jul 23, 9:56 pm, bgelb.mit....@gmail.com wrote:
> Hello -
>
> I am trying to use the Xilinx MIG version 1.72 to generate a working
> interface for the DDR2 memory on the Xilinx ML501 eval board. I am
> having a bit of trouble.
>
> I am able to simulate the controller and testbench just fine using
> ModelSim, but seem to be having issues getting it to work in hardware.
> At the moment, I am simply checking the output of the phy_init_done
> signal, which does not go high at any point, which indicates a problem
> to me. I have not yet been able to delve much deeper into where things
> are getting stuck.
>
> I plan to use ChipScope to try to see what is going on, but I wonder
> before I get too far, if anybody else has tried a similar
> configuration? What experiences (good/bad) have people had with the
> MIG and Virtex-5 DDR2 designs? It would make me feel better if
> somebody out there had gotten it to work - it sounds like - from
> reading this group at least, that there are no shortage of issues with
> this stuff.
>
> Thanks,
> Ben

Did you do a behavioral simulation? Do a post-PAR simulation and check
if the initialization still completes.

Also did you change the controller to work with the ML501? The ML501
has a SODIMM device on it. Check the following link on information on
how to change the controller to work with a SODIMM memory:
http://www.xilinx.com/xlnx/xil_ans_d...PagePath=25040

Jaco

On Jul 24, 11:24 am, "jacob...@xilinx.com" <naude.j...@gmail.com>
wrote:
> On Jul 23, 9:56 pm, bgelb.mit....@gmail.com wrote:
>
>
>
> > Hello -
>
> > I am trying to use the Xilinx MIG version 1.72 to generate a working
> > interface for the DDR2 memory on the Xilinx ML501 eval board. I am
> > having a bit of trouble.
>
> > I am able to simulate the controller and testbench just fine using
> > ModelSim, but seem to be having issues getting it to work in hardware.
> > At the moment, I am simply checking the output of the phy_init_done
> > signal, which does not go high at any point, which indicates a problem
> > to me. I have not yet been able to delve much deeper into where things
> > are getting stuck.
>
> > I plan to use ChipScope to try to see what is going on, but I wonder
> > before I get too far, if anybody else has tried a similar
> > configuration? What experiences (good/bad) have people had with the
> > MIG and Virtex-5 DDR2 designs? It would make me feel better if
> > somebody out there had gotten it to work - it sounds like - from
> > reading this group at least, that there are no shortage of issues with
> > this stuff.
>
> > Thanks,
> > Ben
>
> Did you do a behavioral simulation? Do a post-PAR simulation and check
> if the initialization still completes.
>
> Also did you change the controller to work with the ML501? The ML501
> has a SODIMM device on it. Check the following link on information on
> how to change the controller to work with a SODIMM memory:http://www.xilinx.com/xlnx/xil_ans_d...eID=1&iCountry...
>
> Jaco

Hi Jacob,

Thanks for the reply. I did see the notes on using SODIMMs and believe
I have followed it correctly. I also appropriately modified the
testbench provided with the MIG output - 4 memory modules with 16-bit
datawidth, etc.

I had not run a simulation beyond behavioral. I ran a post-PAR sim
this afternoon and it seems to still simulate correctly (i.e.
phy_init_done) is asserted after ~42us.

I did see some error messages in the modelsim terminal window though:

# ** Error: /afs/csail.mit.edu/proj/redsocs/ISE9.1/verilog/mti_se/
simprims_ver/simprims_ver_source.v(102504): $setup( posedge DI[45] &&&
(wren_enable == 1):3407202 ps, posedge WRCLKL:3407664 ps, 465 ps );

....and later on...

# ** Error: /afs/csail.mit.edu/proj/redsocs/ISE9.1/verilog/mti_se/
simprims_ver/simprims_ver_source.v(100215): $setup( negedge DDLY:
49680022 ps, posedge CLKB:49680321 ps, 305 ps );
# Time: 49680321 ps Iteration: 0 Instance: /ddr2_test_tb/uut_top/
\mint/u_ddr2_top_0/u_mem_if_top_0/u_phy_top_0/u_phy_io_0/
gen_dq[54].u_iob_dq/u_iserdes_dq\

Not sure if these indicate the simulation isn't running properly or
what, but perhaps you can inform me faster than I can figure it out.

Any sense on where to go now? Is there a design that is known to work
on the ML501? I don't really want to use the EDK.

Thanks,
Ben

On Jul 24, 11:24 am, "jacob...@xilinx.com" <naude.j...@gmail.com>
wrote:
> On Jul 23, 9:56 pm, bgelb.mit....@gmail.com wrote:
>
>
>
> > Hello -
>
> > I am trying to use the Xilinx MIG version 1.72 to generate a working
> > interface for the DDR2 memory on the Xilinx ML501 eval board. I am
> > having a bit of trouble.
>
> > I am able to simulate the controller and testbench just fine using
> > ModelSim, but seem to be having issues getting it to work in hardware.
> > At the moment, I am simply checking the output of the phy_init_done
> > signal, which does not go high at any point, which indicates a problem
> > to me. I have not yet been able to delve much deeper into where things
> > are getting stuck.
>
> > I plan to use ChipScope to try to see what is going on, but I wonder
> > before I get too far, if anybody else has tried a similar
> > configuration? What experiences (good/bad) have people had with the
> > MIG and Virtex-5 DDR2 designs? It would make me feel better if
> > somebody out there had gotten it to work - it sounds like - from
> > reading this group at least, that there are no shortage of issues with
> > this stuff.
>
> > Thanks,
> > Ben
>
> Did you do a behavioral simulation? Do a post-PAR simulation and check
> if the initialization still completes.
>
> Also did you change the controller to work with the ML501? The ML501
> has a SODIMM device on it. Check the following link on information on
> how to change the controller to work with a SODIMM memory:http://www.xilinx.com/xlnx/xil_ans_d...eID=1&iCountry...
>
> Jaco

After my post-PAR simulation checked out I decided to check my sanity
and try loading my bitfile on another eval board. It worked! (or at
least phy_init_done gets asserted). Then I reseated the DIMM on the
board I'd been using and it works too. So I guess things are solved
for the moment.

Thanks for the help.

Ben

On Jul 24, 6:01 pm, KF4KJQ <bg...@mit.edu> wrote:
> On Jul 24, 11:24 am, "jacob...@xilinx.com" <naude.j...@gmail.com>
> wrote:
>
>
>
> > On Jul 23, 9:56 pm, bgelb.mit....@gmail.com wrote:
>
> > > Hello -
>
> > > I am trying to use the Xilinx MIG version 1.72 to generate a working
> > > interface for the DDR2 memory on the Xilinx ML501 eval board. I am
> > > having a bit of trouble.
>
> > > I am able to simulate the controller and testbench just fine using
> > > ModelSim, but seem to be having issues getting it to work in hardware.
> > > At the moment, I am simply checking the output of the phy_init_done
> > > signal, which does not go high at any point, which indicates a problem
> > > to me. I have not yet been able to delve much deeper into where things
> > > are getting stuck.
>
> > > I plan to use ChipScope to try to see what is going on, but I wonder
> > > before I get too far, if anybody else has tried a similar
> > > configuration? What experiences (good/bad) have people had with the
> > > MIG and Virtex-5 DDR2 designs? It would make me feel better if
> > > somebody out there had gotten it to work - it sounds like - from
> > > reading this group at least, that there are no shortage of issues with
> > > this stuff.
>
> > > Thanks,
> > > Ben
>
> > Did you do a behavioral simulation? Do a post-PAR simulation and check
> > if the initialization still completes.
>
> > Also did you change the controller to work with the ML501? The ML501
> > has a SODIMM device on it. Check the following link on information on
> > how to change the controller to work with a SODIMM memory:http://www.xilinx.com/xlnx/xil_ans_d...eID=1&iCountry...
>
> > Jaco
>
> After my post-PAR simulation checked out I decided to check my sanity
> and try loading my bitfile on another eval board. It worked! (or at
> least phy_init_done gets asserted). Then I reseated the DIMM on the
> board I'd been using and it works too. So I guess things are solved
> for the moment.
>
> Thanks for the help.
>
> Ben

Came across a weird problem -

I realized that when I was generating the bit file for the ML501
(which seemed to function correctly) I still had the SIM_ONLY
parameter (which disables the 200us start-up delay) set to 1. Things
had been working fine anyway, but I decided to set it to the proper
value of 0. When I do this, the phy_init_done line still gets
asserted, but the error line from the synthesizable testbench also is
asserted. Disabling the 200us delay makes the signal on the error line
disappear. This doesn't make a whole lot of sense to me...

I guess I can run the MIG core with the SIM_ONLY flag forced to 1
since it seems to work, but its a little unsettling to say the least.

Any ideas?

Thanks,
Ben