FPGA Central

In my design, I used the MIG2.3 DDR2 IP Core. In customization, I
chose not to include the DCM inside, and I provide all the necessary
clocks needed by the IP Core.
Now the problem comes at the PAR stage. There is a new PAR warning:

WARNING:Timing:3223 - Timing constraint TS_MC_PHY_INIT_DATA_SEL_90 =
MAXDELAY FROM TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO TIMEGRP "RAMS"
TS_SYS_clk0 * 4; ignored during timing analysis.

This warning is related with the following UCF constraint:

INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM =
"TNM_PHY_INIT_DATA_SEL";
TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL"
TO RAMS "TS_SYS_clk0" * 4;

And I am confused because when choosing DCM inside the IPCore would
not cause this constraint to fail. There is something stranger that I
checked the signal ‘*/u_phy_init/u_ff_phy_init_data_sel’, and I found
that this signal will never drive any BRAMs. Did I get it right or
there is some other points beyond my understanding.

Hello, is there anybody knows what the problem is?
Thank you!