FPGA Central

Hi

I'm using Cyclone II EP2C8 in PQFP208 package and DDR DIMM.
And I'm wondering how to distribute clock signal.
DIMM has 6 clock signals (3 differential pairs).
I figure out two solution:

1. Use differential output PLL_OUT and split signals to three DIMM input.

2. Use 6 general purpose FPGA IO to distribute three pairs of clock and
shifted clock. (This IO pins will be single-ended not differential)

Which soulution is better and will have lower skew to other DDR signals?
Or maybe do that on different way?

--
PGW

On Tue, 9 Oct 2007 18:04:12 +0200, pgw
<"SwietyMikolaj["@]poczta.onet.pl> wrote:

>Hi
>
>I'm using Cyclone II EP2C8 in PQFP208 package and DDR DIMM.
>And I'm wondering how to distribute clock signal.
>DIMM has 6 clock signals (3 differential pairs).
>I figure out two solution:
>
>1. Use differential output PLL_OUT and split signals to three DIMM input.
>
>2. Use 6 general purpose FPGA IO to distribute three pairs of clock and
>shifted clock. (This IO pins will be single-ended not differential)
>
>Which soulution is better and will have lower skew to other DDR signals?
>Or maybe do that on different way?

In Xilinx devices it's quite common to use the DDR output registers in
IOBs, to register the DDR clock in the IOB itself, and reduce skew that
way. I would expect you can do the same in Cyclone but don't know for
sure.

- Brian