FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 06-19-2005, 09:38 AM
Adam Megacz
Guest
 
Posts: n/a
Default damage Atmel AT40k/AT94k with wrong bitstream?


Hey, does anybody know if you can damage Atmel's newer FPGAs with a
bad bitstream (ie vdd-to-ground contention)?

There's no Big Scary Warning in the data sheet (that I could find),
but on the other hand, given the fact that so much of the global
routing is based on pass transistors and they let you create
multi-driver buses, I can't see how they could possibly protect
against this.

This was kind of weird. I know Xilinx has put the Big Scary Warning
on datasheets for parts which actually can't be damaged this way
(covering their ass?), so I'd expect most vendors to err on the side
of caution. Hrm.

Anybody know?

- a

--
"I didn't see it then, but it turned out that getting fired was the
best thing that could have ever happened to me. The heaviness of
being successful was replaced by the lightness of being a beginner
again, less sure about everything. It freed me to enter one of the
most creative periods of my life."

-- Steve Jobs, commencement speech at Stanford, June 2005
Reply With Quote
  #2 (permalink)  
Old 06-19-2005, 06:24 PM
Peter Alfke
Guest
 
Posts: n/a
Default Re: damage Atmel AT40k/AT94k with wrong bitstream?

Just to clarify:
A wrong FPGA bitstream can create massive internal contention, which
can damage a part. (I have seen a puff of smoke coming out of a totally
misconfigured XC3042 15 years ago...)
Xilinx has had CRC protection since XC4000, > 12 years ago. CRC
protects against accidental errors, but does not protect against
feeding a legitimate bitstream, meant for one part type, into the wrong
part type.
To protect against this, the Xilinx bitstream also checks the chip ID.
We have not heard about any problems ever since.
Peter Alfke

Reply With Quote
  #3 (permalink)  
Old 06-20-2005, 09:19 AM
Adam Megacz
Guest
 
Posts: n/a
Default Re: damage Atmel AT40k/AT94k with wrong bitstream?


"Peter Alfke" <[email protected]> writes:
> A wrong FPGA bitstream can create massive internal contention, which


This is not ALWAYS true. It was untrue for the XC6200 sieres:

http://www.fpga-faq.org/archives/10625.html#10627

But that post (which I just found) explains *why*, and I know that the
Atmel chips don't share the same feature (single source per wire).

- a
Reply With Quote
  #4 (permalink)  
Old 06-21-2005, 02:16 PM
Piotr Wyderski
Guest
 
Posts: n/a
Default Re: damage Atmel AT40k/AT94k with wrong bitstream?

Adam Megacz wrote:

> Hey, does anybody know if you can damage Atmel's newer FPGAs with a
> bad bitstream (ie vdd-to-ground contention)?


The same question: is it possible to damage a Cyclone with a bad bitstream?
Remark: it's a feature, not a bug. SRAM-based FPGA devices are too easy
to clone. FPGA manufacturers: why can't you mount two chips inside one
package,
one containing an FPGA and the second one with configuration flash and add
readback fuses, JTAG access fuses etc.? A small amount of EEPROM would
be great too...

Best regards
Piotr Wyderski

Reply With Quote
  #5 (permalink)  
Old 06-21-2005, 04:38 PM
Jon Beniston
Guest
 
Posts: n/a
Default Re: damage Atmel AT40k/AT94k with wrong bitstream?

Lattice XP? One die is much better than two.

Cheers,
Jon

Reply With Quote
  #6 (permalink)  
Old 06-21-2005, 05:34 PM
Piotr Wyderski
Guest
 
Posts: n/a
Default Re: damage Atmel AT40k/AT94k with wrong bitstream?

Jon Beniston wrote:

> Lattice XP?


Or Actel ProASIC. But what about Altera and Xilinx? :-)

> One die is much better than two.


Sure, but I've been told that it is hard to produce flash and FPGA cores
on a single piece of silicon because of technological differences.

Best regards
Piotr Wyderski

Reply With Quote
  #7 (permalink)  
Old 06-25-2005, 08:12 PM
Ulf Samuelsson
Guest
 
Posts: n/a
Default Re: damage Atmel AT40k/AT94k with wrong bitstream?


"Piotr Wyderski" <[email protected]> skrev i meddelandet
news:d990fp$a3g$[email protected]..
> Adam Megacz wrote:
>
>> Hey, does anybody know if you can damage Atmel's newer FPGAs with a
>> bad bitstream (ie vdd-to-ground contention)?

>
> The same question: is it possible to damage a Cyclone with a bad
> bitstream?
> Remark: it's a feature, not a bug. SRAM-based FPGA devices are too easy
> to clone. FPGA manufacturers: why can't you mount two chips inside one
> package,
> one containing an FPGA and the second one with configuration flash and add
> readback fuses, JTAG access fuses etc.? A small amount of EEPROM would
> be great too...
>
> Best regards
> Piotr Wyderski
>


AT94Sxx Secure FPSLIC?


--
A. P. Richelieu


Reply With Quote
  #8 (permalink)  
Old 06-26-2005, 07:51 PM
Adam Megacz
Guest
 
Posts: n/a
Default Re: damage Atmel AT40k/AT94k with wrong bitstream?


"Ulf Samuelsson" <[email protected]> writes:
>>> Hey, does anybody know if you can damage Atmel's newer FPGAs with a
>>> bad bitstream (ie vdd-to-ground contention)?


> AT94Sxx Secure FPSLIC?


Sure; I'm working mainly with the AT94xx, which is just an AT94Sxx
without the EEPROM. Which, in turn, is just an AT40xx plus the AVR
microcontroller. Atmel hasn't really changed their fabric since '98.

- a

--
"I didn't see it then, but it turned out that getting fired was the
best thing that could have ever happened to me. The heaviness of
being successful was replaced by the lightness of being a beginner
again, less sure about everything. It freed me to enter one of the
most creative periods of my life."

-- Steve Jobs, commencement speech at Stanford, June 2005
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Is this wrong behavior? Neo Verilog 7 09-20-2007 06:49 AM
What's wrong with this verilog? Davy Verilog 3 07-04-2005 09:14 AM
what's wrong in this code Sridhar_Gadda Verilog 4 10-12-2004 09:33 PM
What am I doing wrong here? Thomas Womack Verilog 3 10-09-2004 07:02 AM
Atmel DK2 kit onyx FPGA 0 09-17-2004 08:51 PM


All times are GMT +1. The time now is 02:49 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2012, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved