FPGA Central

Hello everyone,

I would like to create a scheme to hook up an external CPU model to a
Verilog design.
I have already established a basic communication protocol to link
Verilog design to an external device.
So, it should be easy to link a CPU model to a Verilog design.

I'm looking for a 32-bit CPU model written in C or Java or Python or
any high-level language that can be supported by gcc.
So far, I can think of are SPARC V8 or DLX CPU, which was designed by
Hennessy and Patterson.
As I don't want to spend time to create development environment for
this, I would like to find a CPU which is ready to plug-in.

The goal of my experiment is to create a framework so that any
external model (CPU, DSP, compression engine, and other IPs) can be
easily plugged in to a Verilog design.

Any comments, any suggestions will be greatly appreciated.

Aki Niimura

On Oct 12, 8:10*pm, akineko <akin...@gmail.com> wrote:
> Hello everyone,
>
> I would like to create a scheme to hook up an external CPU model to a
> Verilog design.
> I have already established a basic communication protocol to link
> Verilog design to an external device.
> So, it should be easy to link a CPU model to a Verilog design.

I do that for YARI, a MIPS compatible processor. Any feature is first
implemented and tested in the ISA level simulator (yarisim). Once that
works, the feature is implemented in the RTL (Verilog) and the two
models are co-simulated on the tests that were used for the ISA level
simulator, as well as more substantial applications.

The cosimulation model I use is decidedly simple: yarisim is run in a
model in which it parses the trace output of the verilog simulation.
This has the advantage of not depending on anything but the ability to
$display() stuff in the RTL model (as opposed to horrible PLI hacks
etc).

For more detail, see http://thorn.ws/yari and/or
http://www.vmars.tuwien.ac.at/php/ps...hp?fileid=1547

Tommy

> I'm looking for a 32-bit CPU model written in C or Java or Python or
> any high-level language that can be supported by gcc.

How accurate does the model need to be?

There are lots of CPU simulators that come as part of GDB.

Cheers,
Jon