 |
FPGA CentralWorld's 1st FPGA Portal |
|
|
09-05-2004, 11:44 AM
|
|||
|
|||
Re: CPLD : Is there a way
Lolotheguru wrote:
> Is there a way to get the schematics of the desing out of the .JED file ! > Is it possible ? Yes. > Thanks and best regards A more usefull question, is : 'is it practical?' You should specify which CPLD, and what other source codes you have from this project. For simpler devices JED2EQN programs exist, and the IC vendors may have internal use JED to EQN - for these you will need to prove ownership of the JED file, and have a credible story as to how you find yourself in the situation where this is necessary. Once you think you have it right, you should be able to prove that. Test vector support can help here. -jg 
|
 |
| Bookmarks |
| Thread Tools | |
| Display Modes | |
Linear Mode
|
|
Similar Threads
|
||||
| Thread | Thread Starter | Forum | Replies | Last Post |
| DPLL in CPLD | Jim | FPGA | 5 | 06-26-2004 10:38 PM |
| CPLD mistery. Help. | lc | FPGA | 6 | 06-22-2004 11:25 PM |
| 5 V inputs to 3.3 V CPLD | Matt Cohen | FPGA | 4 | 06-03-2004 08:02 PM |
| What About CPLD Standardization ? | Chris_S | FPGA | 0 | 07-06-2003 02:21 PM |
All times are GMT +1. The time now is 01:05 AM.
