FPGA Central

Hello eveyone,

I have a design involving a Lattice ispMACH4384. The pinout is already
fixed. I have to make a 5:1 24bit MUX. Unfortunately, the output pins are
all located in GLB H, J and K. As the expert clearly sees, the 24bit MUX
overloads the input signal capabilities of the GLBs (36 max.). So I want to
split up the MUX into two cascaded MUXes. I tried the VHDL attribute
syn_keep, but this is ignored by the fitter tools. How can I prevent the
node collapsing for this 2 MUXes? Iam using ispLEVER with Synplify.

Regards
Falk

Falk Brunner schrieb:
> Hello eveyone,
>
> I have a design involving a Lattice ispMACH4384. The pinout is
already
> fixed. I have to make a 5:1 24bit MUX. Unfortunately, the output pins
are
> all located in GLB H, J and K. As the expert clearly sees, the 24bit
MUX
> overloads the input signal capabilities of the GLBs (36 max.). So I
want to
> split up the MUX into two cascaded MUXes. I tried the VHDL attribute
> syn_keep, but this is ignored by the fitter tools. How can I prevent
the
> node collapsing for this 2 MUXes? Iam using ispLEVER with Synplify.
>
> Regards
> Falk

Why do you want to use the KEEP attribute at all ? What does the fitter
do
you want to prevent, why do you want to prevent that?
Some code?

Rgds
André

If you have a spare i/o pin attach the intermediate mux o/p to that. It is a
dirty trick but usually works. I used to do something like this in the old
days with Intel (later Altera) flexlogic which had a 24V10 structure and
forever was running out of block fan-in signals. I don't often see problem
now with the CPLDs I tend to use.

Similar vein - if you can register an intermediary o/p then you can get the
same result. You can use opposite clock edges if your design uses a clocked
o/p and the device supports if you want to avoid an extra clock latency.

You can also look at synthesiser switches but I'm slightly rusty of Synplify
to tell you exactly the switches.

Taking some of the logic to files lower in your structure and ensuring no
boundry optimisation can work as well.

You can also instantiate components such as final OR for the intermediate
term may also give the desired result.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development
Board.
http://www.enterpoint.co.uk

"Falk Brunner" <[email protected]> wrote in message
news:[email protected]..
> Hello eveyone,
>
> I have a design involving a Lattice ispMACH4384. The pinout is already
> fixed. I have to make a 5:1 24bit MUX. Unfortunately, the output pins are
> all located in GLB H, J and K. As the expert clearly sees, the 24bit MUX
> overloads the input signal capabilities of the GLBs (36 max.). So I want
> to
> split up the MUX into two cascaded MUXes. I tried the VHDL attribute
> syn_keep, but this is ignored by the fitter tools. How can I prevent the
> node collapsing for this 2 MUXes? Iam using ispLEVER with Synplify.
>
> Regards
> Falk
>
>
>

Thanks for the valuable hints. I registered the second MUX on the falling
edge and everything is fine. Quick'n'dirty. ;-)

Regards
Falk