FPGA Central

I had to do something to override the misleading rumor!
Peter Alfke, Xilinx

"Peter Alfke" <[email protected]> schrieb im Newsbeitrag
news:[email protected] oups.com...
>I had to do something to override the misleading rumor!
> Peter Alfke, Xilinx
>

Humm...

I did make full screenshots from the coolrunner webcast that was yesterday.
well I was looking for SDIO related information, the promo for that webcast
specially stated that the use of Xilinx PLDs will be a topic of that
webcast.

So far I have not found the word SDIO on any of the slides of the webcast.
I will look tomorrow how much there is reference to XPLA3.

Antti

PS sorry - Xilinx promo docs have references to SDIO for many years,
but that was always been only words on the presentation slides, this time
I hoped there is some more info, so it is understandable that I was deeply
disappointed. The reference to SDIO in the webcast promo was the only
reason I did take the time to download that stuff at all.

PPS - to my knowledge made public by me small IP core that works
with MMC card (a FPGA configuration IP core) is was the first
open source IP that can be used with the smallest PLDs and does
do something useful with an MMC card. The IP core takes 22 PLDs
cells in XC95 and 21 in Coolrunner - so its the cool thing is really cool.

So seeing as almost only reference to SD/SDIO/MMC at the webcast
a unredable scaled down screenshot from the statemachine from the
CE ATA documentation how to implement a pulse extender to capture
short pulse as interrupt event with Intel XScale ? Not very impressive.

Maybe I should buy speakers and hear the audio of the webcast also

Antti Lukats wrote:
>
> Maybe I should buy speakers and hear the audio of the webcast also

yes

IIRC, one of the questions was about SDIO, so you could
email Jesse Jenkins and ask him.
He did say to email any followups...

-jg

Jesse did answer Antti provtely vi e-mail.
Peter