FPGA Central

I just had a design review on my board and I was zinged for using
resistors to pull the M[2:0] pins to power or ground. I have always
done it that way and do not see a reason to change. But the Xilinx
documents were shown to me, specifically XAPP453, where they clearly
show the pins being pulled hard to power or ground.

I can't find any info in the data sheet on the threshold levels on
these pins (or JTAG), so I can't dispute the argument that I should
follow the app note.

The same person is saying that an XAPP (which I can't find) indicates
that the various JTAG signals need to be pulled low by resistors rather
than high. I have always used resistors to pull TCK and TMS high to
assure that the JTAG port was not put in an invalid state. The TDI and
TDO signals were not important. I am aware that these pins are 2.5
volts. Is that why they are shown pulled to ground, to avoid any
confusion about *which* high? Any official source of info on this?

I have looked on the Xilinx web site, but there are dozens of documents
that score a hit on JTAG and Spartan and I don't see any that answer
the questions.

"rickman" <[email protected]> wrote in message
news:[email protected] oups.com...
>I just had a design review on my board and I was zinged for using
> resistors to pull the M[2:0] pins to power or ground. I have always
> done it that way and do not see a reason to change. But the Xilinx
> documents were shown to me, specifically XAPP453, where they clearly
> show the pins being pulled hard to power or ground.
>
> I can't find any info in the data sheet on the threshold levels on
> these pins (or JTAG), so I can't dispute the argument that I should
> follow the app note.
>
> The same person is saying that an XAPP (which I can't find) indicates
> that the various JTAG signals need to be pulled low by resistors rather
> than high. I have always used resistors to pull TCK and TMS high to
> assure that the JTAG port was not put in an invalid state. The TDI and
> TDO signals were not important. I am aware that these pins are 2.5
> volts. Is that why they are shown pulled to ground, to avoid any
> confusion about *which* high? Any official source of info on this?
>
> I have looked on the Xilinx web site, but there are dozens of documents
> that score a hit on JTAG and Spartan and I don't see any that answer
> the questions.
>

Rick -

You're right about the M[2:0] pins. No reason to get rid of the resistors,
but they're not needed. The only caveat for pulling high is that these pins
are powered by VCCAUX, so pull (or tie) them to 2.5V. As for pull downs,
these pins are weakly pulled up internally, so if you pull them low just
don't use a huge value. Don't read too much into XAPP453. Those are just
logical drawings anyway. (By the way, in Spartan-3E the M[2:0] pins are
general-purpose I/O and are not powered by VCCAUX.)

For the JTAG pins, read record #11433 in the Xilinx answers database. It
says to pull TMS and TDI high through 4.7K and let TCK float. I usually see
TCK also pulled high, but with TMS high it shouldn't matter. Again, though,
the JTAG pins are powered by VCCAUX, so pull to +2.5V unless you follow the
guidelines to support 3.3V configuration.

Rob

RobJ wrote:
> "rickman" <[email protected]> wrote in message
> news:[email protected] oups.com...
> >I just had a design review on my board and I was zinged for using
> > resistors to pull the M[2:0] pins to power or ground. I have always
> > done it that way and do not see a reason to change. But the Xilinx
> > documents were shown to me, specifically XAPP453, where they clearly
> > show the pins being pulled hard to power or ground.
> >
> > I can't find any info in the data sheet on the threshold levels on
> > these pins (or JTAG), so I can't dispute the argument that I should
> > follow the app note.
> >
> > The same person is saying that an XAPP (which I can't find) indicates
> > that the various JTAG signals need to be pulled low by resistors rather
> > than high. I have always used resistors to pull TCK and TMS high to
> > assure that the JTAG port was not put in an invalid state. The TDI and
> > TDO signals were not important. I am aware that these pins are 2.5
> > volts. Is that why they are shown pulled to ground, to avoid any
> > confusion about *which* high? Any official source of info on this?
> >
> > I have looked on the Xilinx web site, but there are dozens of documents
> > that score a hit on JTAG and Spartan and I don't see any that answer
> > the questions.
> >
>
> Rick -
>
> You're right about the M[2:0] pins. No reason to get rid of the resistors,
> but they're not needed. The only caveat for pulling high is that these pins
> are powered by VCCAUX, so pull (or tie) them to 2.5V. As for pull downs,
> these pins are weakly pulled up internally, so if you pull them low just
> don't use a huge value. Don't read too much into XAPP453. Those are just
> logical drawings anyway. (By the way, in Spartan-3E the M[2:0] pins are
> general-purpose I/O and are not powered by VCCAUX.)
>
> For the JTAG pins, read record #11433 in the Xilinx answers database. It
> says to pull TMS and TDI high through 4.7K and let TCK float. I usually see
> TCK also pulled high, but with TMS high it shouldn't matter. Again, though,
> the JTAG pins are powered by VCCAUX, so pull to +2.5V unless you follow the
> guidelines to support 3.3V configuration.

This answers record is the sort of thing I was looking for. I do find
it bizzar that they say to not bother with tieing TCK high. I thought
*ALL* CMOS inputs should be tied high or low to prevent them from
sitting in the middle and drawing higher currents.

I have an email into one of the Xilinx FAEs here. We'll see what he
has to say. When you need one of the Xilinx guys they can be hard to
find.

I just found where they spec the IO signals used for configuration. In
the table for the various IO standard, the row for LVCMOS25 has a
footnote that says this is the standard used for the dedicated
configuration IOs. So it is in the data sheet, but you have to know
where to look for it.

Someone might consider making this easier to find. It should be
somewhere that it can be found when looking for the signal group rather
than having to know to look for the IO standard and then finding the
footnote.


rickman wrote:
> I just had a design review on my board and I was zinged for using
> resistors to pull the M[2:0] pins to power or ground. I have always
> done it that way and do not see a reason to change. But the Xilinx
> documents were shown to me, specifically XAPP453, where they clearly
> show the pins being pulled hard to power or ground.
>
> I can't find any info in the data sheet on the threshold levels on
> these pins (or JTAG), so I can't dispute the argument that I should
> follow the app note.
>
> The same person is saying that an XAPP (which I can't find) indicates
> that the various JTAG signals need to be pulled low by resistors rather
> than high. I have always used resistors to pull TCK and TMS high to
> assure that the JTAG port was not put in an invalid state. The TDI and
> TDO signals were not important. I am aware that these pins are 2.5
> volts. Is that why they are shown pulled to ground, to avoid any
> confusion about *which* high? Any official source of info on this?
>
> I have looked on the Xilinx web site, but there are dozens of documents
> that score a hit on JTAG and Spartan and I don't see any that answer
> the questions.

RobJ wrote:
> You're right about the M[2:0] pins. No reason to get rid of the resistors,
> but they're not needed. The only caveat for pulling high is that these pins
> are powered by VCCAUX, so pull (or tie) them to 2.5V. As for pull downs,
> these pins are weakly pulled up internally, so if you pull them low just
> don't use a huge value. Don't read too much into XAPP453. Those are just
> logical drawings anyway. (By the way, in Spartan-3E the M[2:0] pins are
> general-purpose I/O and are not powered by VCCAUX.)

But if M[2:0] can be outputs, you really *should* use resistors, right?
If you misconfigure the FPGA you could have outputs driving gnd or
power.

Alan Nishioka

"Alan Nishioka" <[email protected]> wrote in message
news:[email protected] oups.com...
> RobJ wrote:
>> You're right about the M[2:0] pins. No reason to get rid of the
>> resistors,
>> but they're not needed. The only caveat for pulling high is that these
>> pins
>> are powered by VCCAUX, so pull (or tie) them to 2.5V. As for pull downs,
>> these pins are weakly pulled up internally, so if you pull them low just
>> don't use a huge value. Don't read too much into XAPP453. Those are just
>> logical drawings anyway. (By the way, in Spartan-3E the M[2:0] pins are
>> general-purpose I/O and are not powered by VCCAUX.)
>
> But if M[2:0] can be outputs, you really *should* use resistors, right?
> If you misconfigure the FPGA you could have outputs driving gnd or
> power.
>
> Alan Nishioka
>

That only applies to Spartan-3E. On Spartan-3, which the OP was asking
about, the M[2:0] pins are dedicated configuration inputs powered from
VCCAUX. But even in Spartan-3E, the pins can only be outputs if you use them
in your design as outputs. If they are not used they default to inputs with
weak pullups after configuration like all other unused I/O, in which case
direct connection to power or GND is fine. And if they ARE used as
functional pins you obviously would NOT tie them to power or GND. It all
works out in the end.

Rob

rickman wrote:
> I just had a design review on my board and I was zinged for using
> resistors to pull the M[2:0] pins to power or ground. I have always
> done it that way and do not see a reason to change. But the Xilinx
> documents were shown to me, specifically XAPP453, where they clearly
> show the pins being pulled hard to power or ground.

For Spartan-3 FPGAs, it is perfectly acceptable to tie the M[2:0] pins
directly to either VCCAUX (2.5V) or to GND. External pull-up or
pull-down resistors are also acceptable, but not required. I tend to
use external pull-ups or pull-downs as it allows me to override the
default FPGA configuration mode on the board. In some systems, this
may be desirable for field diagnostics, etc.

On Spartan-3E FPGAs, the M[2:0] pins _can_ be user-I/O after
configuration. If using these pins as user-I/O, then you definitely
want to use pull-up or pull-down resistors.

BTW, the mode pins have internal pull-up resistors that are active
during configuration. If left floating externally, the M[2:0] mode
pins will see "111" and the FPGA will be in Slave Serial configuration
mode.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/-3E FPGAs
http://www.xilinx.com/spartan3e
---------------------------------
The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.

The JTAG interface on Spartan-3 FPGAs are powered by the VCCAUX (2.5V)
supply.

The key limitation is to avoid back-driving the JTAG inputs. For
example, if you apply a 3.3V input to a JTAG input, then there will be
a path back through the ESD protection diode.

There are a variety of solutions here, depending on your specific
application.

1. If driving the JTAG interface with 2.5V, no problem.

2. If actively driving the JTAG interface with 3.3V, be sure to use
current-limiting series resistors and it is best to park the lines low
or let them float when not in use. You can also three-state the JTAG
pins after configuration or drive them using open-drain outputs. The
JTAG pins have dedicated pull-up resistors to VCCAUX during
configuration. After configuration, these pull-up resistors are left
enabled by default. Via bitstream options, you can also change these
to pull-down resistors or turn them off.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/-3E FPGAs
http://www.xilinx.com/spartan3e
---------------------------------
The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.

There is one engineer on our team who is a real PITA. He is always
kibitzing other people's designs for trivial things that no one else
thinks is worth mentioning. These resistor issues is one of those
things. Just so I don't have to change the parts on my schematic, can
I get you to explicitly say it is ok to use pullups to 2.5 volts of up
to 10k ohms on the various signals lines powered by VCCAUX?

I can't believe he is trying to say the direct connection shown in the
3.3 volt configuration guide is an indication that we should not be
using pull up resistors. But the process we use for design requires me
to consider his input and justify my decision. His only reason for
making that assertion is the digram in the app note which shows direct
connections.


Steve Knapp (Xilinx Spartan-3 Generation FPGAs) wrote:
> The JTAG interface on Spartan-3 FPGAs are powered by the VCCAUX (2.5V)
> supply.
>
> The key limitation is to avoid back-driving the JTAG inputs. For
> example, if you apply a 3.3V input to a JTAG input, then there will be
> a path back through the ESD protection diode.
>
> There are a variety of solutions here, depending on your specific
> application.
>
> 1. If driving the JTAG interface with 2.5V, no problem.
>
> 2. If actively driving the JTAG interface with 3.3V, be sure to use
> current-limiting series resistors and it is best to park the lines low
> or let them float when not in use. You can also three-state the JTAG
> pins after configuration or drive them using open-drain outputs. The
> JTAG pins have dedicated pull-up resistors to VCCAUX during
> configuration. After configuration, these pull-up resistors are left
> enabled by default. Via bitstream options, you can also change these
> to pull-down resistors or turn them off.
> ---------------------------------
> Steven K. Knapp
> Applications Manager, Xilinx Inc.
> General Products Division
> Spartan-3/-3E FPGAs
> http://www.xilinx.com/spartan3e
> ---------------------------------
> The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.

"rickman" <[email protected]> wrote in message
news:[email protected] oups.com...
> There is one engineer on our team who is a real PITA. He is always
> kibitzing other people's designs for trivial things that no one else
> thinks is worth mentioning. These resistor issues is one of those
> things. Just so I don't have to change the parts on my schematic, can
> I get you to explicitly say it is ok to use pullups to 2.5 volts of up
> to 10k ohms on the various signals lines powered by VCCAUX?
>
> I can't believe he is trying to say the direct connection shown in the
> 3.3 volt configuration guide is an indication that we should not be
> using pull up resistors. But the process we use for design requires me
> to consider his input and justify my decision. His only reason for
> making that assertion is the digram in the app note which shows direct
> connections.
>
>

I think I know that guy!!

Everything you need to know to justify your design is in the data sheet. If
people knew who writes most app notes in our business they wouldn't treat
them with such veneration. Slap that PITA for me!!

Rob

There are two good and two marginal reasons to use external pull-up
resistors instead of a short circuit to Vcc.:

If the pin is dual-use and might also be input or output (that's
obvious)

If you want to change the level for testing purposes, by shortening it
to ground.

If you are an old TTL guy who remembers that LS-TTL inputs could be
damaged by a very high Vcc. (historical-hysterical reason).

If you think a resistor is dirt-cheap and buys you some flexibility or
peace of mind.

Peter Alfke, Xilinx, from home.

Peter Alfke wrote:
> There are two good and two marginal reasons to use external pull-up
> resistors instead of a short circuit to Vcc.:
>
> If the pin is dual-use and might also be input or output (that's
> obvious)
>
> If you want to change the level for testing purposes, by shortening it
> to ground.
>
> If you are an old TTL guy who remembers that LS-TTL inputs could be
> damaged by a very high Vcc. (historical-hysterical reason).
>
> If you think a resistor is dirt-cheap and buys you some flexibility or
> peace of mind.

... and another testing use, is to use the pin to bring out an
internal signal, for probing.
- ie I'd add a resistor _and_ a probe pad.
[ you also then side-step his input, as now your use is
clearly not in that appnote ]

> .. and another testing use, is to use the pin to bring out an
> internal signal, for probing.
> - ie I'd add a resistor _and_ a probe pad.
> [ you also then side-step his input, as now your use is
> clearly not in that appnote ]


I've just noticed this thread.

When I worked for Nortel in Belfast the manufacturing guys didn't
like it if _any_ non power pins were hard assigned to power or
ground as it stopped them using the flying probe tester to test
boards after manufacture.

Do you know who's going to be building/testing your boards 5 years
down the line?

As the others have said using resistors adds a bit of flexibility
during debug and allows a much easier cut and strap to fix things
if you ever make a schematic mistake (not that any of us ever do!).


Nial

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