FPGA Central

Hi,

I have routed an input clock from an input pin directecly to an output
pin
and I used this clock (too) to all my design under a Stratix FPGA.

We have encountered a big problem because the input clock signal fall
under 0.5 V !!!

So for this, we have just divided the input clock to two disctinct
input pin (one input pin toward one output pin) and the other input pin
to our design and that works fine

Why we cannot send an clock signal (from an input pin) to an output pin
and to the entire design ?

Do you know what's happen ?

Thanks.

Why do you not use a PLL within the FPGA ?

You could use the output C0 or C1 of the PLL for FPGA "inner" purposes
and
the output E to route the clock to an output pin.

Rgds
André