FPGA Central

Hi,
I'm trying to implement a design where signals are fed to the
Xilinx CoolRunner XPLA3 CPLD from a USB card. All signals are
controlled via JavaScript and ActiveX control (including clock), thus
making timing between signals being adjustable - from 100 miliseconds
to seconds. There are 4 signals - DataIn, Reset, Ready, and Clock. As
tested in the simulator, after the first clock cycle when reset is 0
and ready is 1, the outputs should be 1. However, in reality, all
outputs remain 0. I have tested the board and the connections to the
CPLD with a test lead - all the signals reach it. The CPLD is powered
by 3.3V and the signals are 5V (all withing specs, as far as I see),
and can be programmed without a problem. The clock signal is connected
to pin 2 of the CPLD. Can someone explain why I am facing this
problem, or has any solution for it?
-Gregory Titievsky