FPGA Central

Hi

I need some help with 'ChipScope Pro 6.3i inserter' in ISE 6.3.

As an exercise, I want to insert 'logic analyzer(ILA)' to simple
'counter' (below).

With respect to the user guide, I did was the following,

In ISE 6.3
* Implementation
* Bitstream generation and configuration on V2pro. ('counter.bit' - it
seems okay)

After that, in 'ChipScope Pro Inserter' setting
* Input trigger setting : 3 triggers
- One port for 'reset' signal(width 1), one port for 'count'
signal(width 1), one port for 'Q' output signal (width 4) )
- Match type : 'Basic w/edge' type
- Data type : "Data Same as Trigger"
* Connect
- 'clock port' to 'CH0:clock_BUFGP'
- 'trig0' to 'CH0:count_IBUF'
- 'trig1' to 'CH0:reset_IBUF'
- 'trig2' to 'CH0:Q_tmp_n0000<3>,
'CH0:Q_tmp_n0000<2>,
'CH0:Q_tmp_n0000<1>,
'CH0:Q_tmp_n0000<0>
- Insert ('counter.cdc' - it seems okay, but not quite sure)

After that, in 'ChipScope Pro Analyzer'
* Jtag Chain -> cable selection
* To configure FPGA, load 'counter.bit' to device 2.
* To import project file, load 'counter.cdc'

Then finally some waveform appears.

Problem is that I do not know how to set up 'input trigger ports' (in
this case, 'count_IBUF', 'reset_IBUF', 'Q_tmp_n0000' - 5 signals ).

We need some input vectors (something like 'test vector' in
simulation). So far I could not find how to do that in user guide.

Thankyou for reading and some comment too

regards

----------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port( clock: in std_logic;
reset: in std_logic;
count: in std_logic; -- counter : enable
Q: out std_logic_vector(3 downto 0)
);
end counter;

architecture behv of counter is
signal Q_tmp: std_logic_vector(3 downto 0);
begin
Q <= Q_tmp;
process(clock, count, reset)
begin
if reset = '1' then
Q_tmp <= "0000";
elsif (clock='1' and clock'event) then
if count = '1' then
Q_tmp <= Q_tmp + '1';
end if;
end if;
end process;
end behv;
------------------------------------------------------

"pasacco" <[email protected]> schrieb im Newsbeitrag
news:[email protected] ups.com...
> Hi
>
> I need some help with 'ChipScope Pro 6.3i inserter' in ISE 6.3.
>
> As an exercise, I want to insert 'logic analyzer(ILA)' to simple
> 'counter' (below).
>
> With respect to the user guide, I did was the following,
>
> In ISE 6.3
> * Implementation
> * Bitstream generation and configuration on V2pro. ('counter.bit' - it
> seems okay)
>
> After that, in 'ChipScope Pro Inserter' setting
> * Input trigger setting : 3 triggers
> - One port for 'reset' signal(width 1), one port for 'count'
> signal(width 1), one port for 'Q' output signal (width 4) )
> - Match type : 'Basic w/edge' type
> - Data type : "Data Same as Trigger"
> * Connect
> - 'clock port' to 'CH0:clock_BUFGP'
> - 'trig0' to 'CH0:count_IBUF'
> - 'trig1' to 'CH0:reset_IBUF'
> - 'trig2' to 'CH0:Q_tmp_n0000<3>,
> 'CH0:Q_tmp_n0000<2>,
> 'CH0:Q_tmp_n0000<1>,
> 'CH0:Q_tmp_n0000<0>
> - Insert ('counter.cdc' - it seems okay, but not quite sure)
>
> After that, in 'ChipScope Pro Analyzer'
> * Jtag Chain -> cable selection
> * To configure FPGA, load 'counter.bit' to device 2.
> * To import project file, load 'counter.cdc'
>
> Then finally some waveform appears.
>
> Problem is that I do not know how to set up 'input trigger ports' (in
> this case, 'count_IBUF', 'reset_IBUF', 'Q_tmp_n0000' - 5 signals ).
>
> We need some input vectors (something like 'test vector' in
> simulation). So far I could not find how to do that in user guide.
>
> Thankyou for reading and some comment too
>
> regards
>
> ----------------------------------------------------
> library ieee ;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_unsigned.all;
>
> entity counter is
> port( clock: in std_logic;
> reset: in std_logic;
> count: in std_logic; -- counter : enable
> Q: out std_logic_vector(3 downto 0)
> );
> end counter;
>
> architecture behv of counter is
> signal Q_tmp: std_logic_vector(3 downto 0);
> begin
> Q <= Q_tmp;
> process(clock, count, reset)
> begin
> if reset = '1' then
> Q_tmp <= "0000";
> elsif (clock='1' and clock'event) then
> if count = '1' then
> Q_tmp <= Q_tmp + '1';
> end if;
> end if;
> end process;
> end behv;
> ------------------------------------------------------
>

its only you yourseld who knows on what event you want to trigger.
just select the 1 0 R F B or in the trigger setting and arm the ILA

Antti
BTW I dont understand why you defined 3 trigger ports not one, doesnt seem
to make sense in this example.

Hi

I am trying hard that 4 bit counter example with no luck so far --:

I changed into the following

In ILA Inserter
* Trigger port :
- number of port = 1, width = 1
* Match function :
- number of match unit = 2, match type = basic
* Port connection
- clock port <= 'clock' signal (CH0)
- trigger port <= 'count' signal (CH0)
- data port <= 'Q' signal (CH0,CH1,CH2,CH3)

In Analyzer
* Trigger setup : 2 match function definition
- M0 == '0', M1 == '1' /* I am not
skillful at this part part */
- Trigger condition sequence (2) : M0 -> M1 /* I am not skillful at
this part part */

My intention for the test vector is that
- We give a stimulus to 'count' port, using 2 match functions - " 0, 1,
....." (seqence of 2)

The result is that
- In waveform : data port<0> is always '1', the other ports are all '0'

What the command window says is that
--------------------------
COMMAND: reset_trigger_settings 2 0
COMMAND: set_window_capture 2 0 0 1 512 0
COMMAND: set_trigger_condition 2 0 1 1 FFFF
COMMAND: set_storage_condition 2 0 FFFF
COMMAND: run 2 0
COMMAND: upload 2 0
INFO - Device 2 Unit 0: Waiting for core to be armed
---------------------------

It seems that 'analyzer' part is wierd,
What is the problem ?

thankyou in advance

try this link:

http://www.xilinx.com/products/softw...pe_ila_tut.pdf

it helped me a lot

cheers

Hi

Thankyou for pointer. That document is quite nice.
I followed the tutorial (Inserter and Analyzer) and got the (more ore
less -- same waveform as the tutorial.

ISE/ChipScopePro 6.3 has following differences (compared to version
4.2) among others.
- In 'Inserter', there is no ' Extended matching' button in 'Match
setting' -----> So I ignored it.
- In 'Inserter', 'data depth' is minimally '512' -----> So I chose
512.
- In 'Analyzer', there is no 'match length type' and 'match length
value' in 'Trigger setting' -----> So i ignored it.
- In 'Analyzer', there is no 'capture type' -----> So i
ignored it.

The waveform says that the counter logic is okay.
Problem is that
- The waveform starts with the counter value "0011 0110 0101 0010"
(with setting depth=512, position=100)
- At time '0', the counter value is "0011 0110 1011 0110", meaning
first value + 100

Is it problematic?

BTW, I have two things unclear for me about 'match value' and
'position' in 'Trigger setup'.

Regarding the trigger condition : "00000001" < 2 match functions <
"00000011"
- Is it correct that we make this condition in order to consider the 2
cycles of 'ILA' latency ?

Regarding 'position'
- In my case, . But in 'position' 100 (as indicated in the tutorial),
the counter value is not "0000 0000 0000 0010", which was expected from
the tutorial.

Anyway I wish to have "0000 0000 0000 0010" at time step '0'.

Thankyou again Regards

Hi

Some trial and error (one match function == 2) for 4 bit counter case,
now counter value is "0010" at time 0 (position=0).
So it seems problem is solved.
Thankyou again for comment and nice pointer. Regards

anytime

Hi

Let me continue this discussion.

In case, we have additional input ports (signals), for example, "reset"
or some "enable" ports, it seems that "ILA" and "Analyzer" are not
enough for the on-chip verfication.
It seems that we need "VIO" core as a input signal generation. Is it
correct?

Can we verify the logic with only "ILA" and "Analyzer" in this case ?

Thankyou again, Regards

you probably can, but i am suggesting to use VIO.
first, its probably easier.
second its a lot of fun

you can instantiate it in a pretty similar manner as the previous two.

just make ICON with two control ports and connect as an example below.
though if you are using VIO you have to remove all your inputs and make
them as internal signals and then connect them to VIO. otherwise it
will give you an error message.

here's an example, good luck

entity top is
port (
clk : in std_logic;

cnt : out std_logic_vector(7 downto 0);
cost1 : out std_logic_vector(COST_SIG-1 downto 0));

end top;

architecture Behavioral of top is


-----------------------------------------------------------------------------
-- instatiating ICON

-----------------------------------------------------------------------------
signal control_bus0 : std_logic_vector(35 downto 0);
signal control_bus1 : std_logic_vector(35 downto 0);

component icon
port(
control0 : out std_logic_vector(35 downto 0);
control1 : out std_logic_vector(35 downto 0));
end component;


-----------------------------------------------------------------------------
-- instatiating VIO

-----------------------------------------------------------------------------
signal async_in : std_logic_vector(199 downto 0);
signal async_out : std_logic_vector(199 downto 0);

component vio
port(
control : in std_logic_vector(35 downto 0);
async_in : in std_logic_vector(199 downto 0);
async_out : out std_logic_vector(199 downto 0));
end component;


-----------------------------------------------------------------------------
-- instatiating ILA

-----------------------------------------------------------------------------
signal data : std_logic_vector(255 downto 0);
signal trig0 : std_logic_vector(0 downto 0);
signal trig1 : std_logic_vector(4 downto 0);
signal trig2 : std_logic_vector(0 downto 0);

component ila
port(
control : in std_logic_vector(35 downto 0);
clk : in std_logic;
data : in std_logic_vector(255 downto 0);
trig0 : in std_logic_vector(0 downto 0);
trig1 : in std_logic_vector(4 downto 0);
trig2 : in std_logic_vector(0 downto 0));
end component;

-----------------------------------------------------------------------------

begin


-----------------------------------------------------------------------------
-- instatiating ICON

-----------------------------------------------------------------------------
i_icon : icon port map(
control0 => control_bus0,
control1 => control_bus1);


-----------------------------------------------------------------------------
-- instatiating VIO

-----------------------------------------------------------------------------

-- connect things that i want to control to async_out
-- (inputs)
process (async_out)
begin
vio_data_in(73 downto 0) <= async_out(199 downto 126);

end process;

-- here async_in gets signals that are coming out
-- (outputs)
async_in(0) <= cnt_sig(0);

i_vio : vio port map(
CONTROL => control_bus0,
async_in => async_in,
async_out => async_out);


-----------------------------------------------------------------------------
-- instatiating ILA

-----------------------------------------------------------------------------

-- here assign triggers
trig0(0) <= read_mem_sig;

-- here assign data
data(79 downto 64) <= cost_2;

i_ila : ila port map(
control => control_bus1,
clk => clk,
data => data,
trig0 => trig0,
trig1 => trig1,
trig2 => trig2);

-----------------------------------------------------------------------------

end Behavioral;

Hi

I need some more help --:

Based on original counter (VHDL 1) and your template (VHDL 2, Thankyou
.....VIO, ILA, ICON are generated.
It is not clear for me to how to make VIO work --:

My goal is
- to drive "internal reset input signal" to <'1' ---> '0'> (or '0' from
beginning) using VIO and
- to see the proper waveform in 'Analyzer'.

It seems that it is problematic for VIO to add virtual input to
internal reset signal.

Thankyou again for the help. Regards

BTW, Mapping process does not create any warning, while synthesis
process generates following warnings.

================================================== =======================
* Low Level Synthesis
*
================================================== =======================
Launcher: "ila.ngo" is up to date.
Launcher: "vio.ngo" is up to date.
Launcher: "icon.ngo" is up to date.
WARNING:Xst:1474 - Core <ila> was not loaded for <i_ila> as one or more
ports did not line up with component declaration. Declared input port
<control<35>> was not found in the core. Please make sure that
component declaration ports are consistent with the core ports
including direction and bus-naming conventions.
WARNING:Xst:1474 - Core <vio> was not loaded for <i_vio> as one or more
ports did not line up with component declaration. Declared input port
<control<35>> was not found in the core. Please make sure that
component declaration ports are consistent with the core ports
including direction and bus-naming conventions.
WARNING:Xst:1474 - Core <icon> was not loaded for <i_icon> as one or
more ports did not line up with component declaration. Declared output
port <control0<3>> was not found in the core. Please make sure that
component declaration ports are consistent with the core ports
including direction and bus-naming conventions.
WARNING:Xst:1291 - FF/Latch <counter_35> is unconnected in block <top>.
WARNING:Xst:1291 - FF/Latch <counter_32> is unconnected in block <top>.
WARNING:Xst:1291 - FF/Latch <counter_33> is unconnected in block <top>.
WARNING:Xst:1291 - FF/Latch <counter_34> is unconnected in block <top>.



*********** VHDL 1
************************************************** *********
---------------------------------------------------------------------------------------------
-- Design under "simulation"
-- Original 4 bit (internally 36bit) counter
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity top is
port
(
clk : in std_logic;
cnt : out std_logic_vector(3 downto 0)
);
end top;

architecture behave of top is
signal counter : std_logic_vector(35 downto 0):= (others => '0');
signal rst_tmp: std_logic:='0'; -- internal reset signal
begin
process(rst_tmp,clk)
begin
if rst_tmp='1' then
counter <= (others => '0');
elsif ( clk'event and clk = '1' ) then
counter <= counter + 1;
end if;
end process;
cnt <= counter(31 downto 28);
end behave;
-------------------------------------------------------------------------------


******* VHDL 2 ************************************************
----------------------------------------------------------------------
-- Design under Verification
-- 4 bit counter (internally 36 bit counter)
-- With internal "reset" input signal
-- VIO, ICON, ILA : Core generated
--------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity top is
port
(
clk : in std_logic;
cnt : out std_logic_vector(3 downto 0)
);
end top;

architecture behave of top is
signal counter : std_logic_vector(35 downto 0):= (others => '0');
signal rst_tmp : std_logic:='0';

--- ICON declaration ------------------------------------
signal control0 : std_logic_vector(35 downto 0);
signal control1 : std_logic_vector(35 downto 0);
component icon
port
( control0 : out std_logic_vector(35 downto 0);
control1 : out std_logic_vector(35 downto 0) );
end component;
--------------------------------------------------------

--- ILA declaration ------------------------------------
signal data : std_logic_vector(3 downto 0);
signal trig0 : std_logic_vector(3 downto 0);
component ila
port
( control : in std_logic_vector(35 downto 0);
clk : in std_logic;
data : in std_logic_vector(3 downto 0);
trig0 : in std_logic_vector(3 downto 0) );
end component;
--------------------------------------------------------

---- VIO declarations ----------------------------------
signal sync_in : std_logic_vector(3 downto 0);
signal async_out : std_logic_vector(0 downto 0);
component vio
port
( control : in std_logic_vector(35 downto 0);
clk : in std_logic;
async_out : out std_logic_vector(0 downto 0);
sync_in : in std_logic_vector(3 downto 0) );
end component;
---------------------------------------------------------

begin
process(rst_tmp,clk)
begin
if rst_tmp='1' then
counter <= (others => '0');
elsif ( clk'event and clk = '1' ) then
counter <= counter + 1;
end if;
end process;

cnt <= counter(31 downto 28);

---- ICON instantiation -------------
i_icon : icon
port map
( control0 => control0,
control1 => control1 );
--------------------------------------

--- ILA instantiation ------------
trig0(0) <= counter(0);
trig0(1) <= counter(1);
trig0(2) <= counter(2);
trig0(3) <= counter(3);
data(0) <= counter(0);
data(1) <= counter(1);
data(2) <= counter(2);
data(3) <= counter(3);

i_ila : ila
port map
( control => control0,
clk => clk,
data => data,
trig0 => trig0 );
-----------------------------------

---- VIO intantiation -------------
rst_tmp <= async_out(0); -- this part is wierd

sync_in(0) <= counter(0);
sync_in(1) <= counter(1);
sync_in(2) <= counter(2);
sync_in(3) <= counter(3);

i_vio : vio
port map
( control => control1,
clk => clk,
async_out => async_out,
sync_in => sync_in );
-----------------------------------

end behave;
************************************************** **************

When I change the code below as shown below,
(i.e., rst_tmp = 0),
anyway it seems okay, though there are some warning messages.
I need to play with this more

-------------------------------------
rst_tmp <= async_out(0);
==>
rst_tmp <= async_out(0);
async_out(0) <= '0';
-------------------------------------

Thanks a lot for the comments and nice template too. Regards

in my example all the things connected to async out are within the
process which is sensitive to async_out.

try this:

process(async_out)
begin
rst_tmp <= async_out(0);
end process;

other things seem to be fine

Hi

Now the 'counter' example is working. ChipScope Pro is very handy.

Umm....I never had used a logic analyzer. And the VHDL code (what I
implemented last 3 months) is not working well with ChipScope Pro --:
Most probably it should be design problems.

BTW, to better understand how ChipScope Pro works, let me ask some more
things.

* In manual (ug029), it is written "VIO can both monitor and drive
interval FPGA signals in real time".
As far as I understand, we can 'drive' internal signal using
'async_out'.
Questions are
- Can we 'drive' signals in real time in 'Analyzer' ? If yes, should
we use 'trigger' setup and 'match function' to do that?
- In my 'counter' example, I forced rst_tmp (reset signal) to '0'
using the code below. I wonder this is a right way to 'drive' internal
signal in ChipScope Pro.
-----------------------------------------------------------------------------
process(async_out)
begin
rst_tmp <= async_out(0);
end process;
async_out(0) <= '0'; -- to force 'rst_tmp' signal to '0'
-------------------------------------------------------------------------------

Thankyou. Regards

Hi

Now the 'counter' example is working. ChipScope Pro is very handy.

Umm....I never had used a logic analyzer. And the VHDL code (what I
implemented last 3 months) is not working well with ChipScope Pro --:
Most probably it should be design problems.

BTW, to better understand how ChipScope Pro works, let me ask some more
things.

* In manual (ug029), it is written "VIO can both monitor and drive
interval FPGA signals in real time".
As far as I understand, we can 'drive' internal signal using
'async_out'.
Questions are
- Can we 'drive' signals in real time in 'Analyzer' ? If yes, should
we use 'trigger' setup and 'match function' to do that?
- In my 'counter' example, I forced rst_tmp (reset signal) to '0'
using the code below. I wonder this is a right way to 'drive' internal
signal in ChipScope Pro.
-----------------------------------------------------------------------------
process(async_out)
begin
rst_tmp <= async_out(0);
end process;
async_out(0) <= '0'; -- to force 'rst_tmp' signal to '0'
-------------------------------------------------------------------------------

Thankyou. Regards

Hi

Now the 'counter' example is working. ChipScope Pro is very handy.

Umm....I never had used a logic analyzer. And the VHDL code (what I
implemented last 3 months) is not working well with ChipScope Pro --:
Most probably it should be design problems.

BTW, to better understand how ChipScope Pro works, let me ask some more
things.

* In manual (ug029), it is written "VIO can both monitor and drive
interval FPGA signals in real time".
As far as I understand, we can 'drive' internal signal using
'async_out'.
Questions are
- Can we 'drive' signals in real time in 'Analyzer' ? If yes, should
we use 'trigger' setup and 'match function' to do that?
- In my 'counter' example, I forced rst_tmp (reset signal) to '0'
using the code below. I wonder this is a right way to 'drive' internal
signal in ChipScope Pro.
-----------------------------------------------------------------------------
process(async_out)
begin
rst_tmp <= async_out(0);
end process;
async_out(0) <= '0'; -- to force 'rst_tmp' signal to '0'
-------------------------------------------------------------------------------

Thankyou. Regards

i have no idea. i am new in these things as well. try it and see what
happens.
cheers

Hi

Yes, actually, I just there are some simulation problems with
post-synthesis simulation in my design
Anyway thankyou for introducing good documents and examples.
Cheers.